Self-correction method of multi-device data synchronization

Abstract

The invention discloses a self-correction method of multi-device data synchronization. By adjusting the delay of a BUFR reset signal in an FPGA in a ADC test mode, performing consistency judgment on multiple paths of data output by a multi-core ADC, and performing statistical analysis on the results to obtain an optimal delay set value, the synchronization between ADC multi-core data is ensured;on the basis, the delay of the ADC reset signal is continuously adjusted, the relationship between the ADC reset signal and a sampling clock SCLK is judged by changing the optimal delay set value of aBUFR synchronous reset signal, and an optimal delay value of the ADC reset signal is obtained at last to ensure the stability of the ADC reset; and finally, the value of an ADC synchronization register is adjusted by judging the sampling data of each ADC in the test mode to ensure the synchronization between multiple ADCs, thus achieving stable integration of the data between the multiple ADCs and improving the sampling rate of a collection system.

Description

technical field [0001] The invention belongs to the technical field of digital signal processing, and more specifically relates to a multi-device data synchronization self-calibration method. Background technique [0002] With the rapid development of science and technology, the complexity of the signal is increasing day by day, and the requirements for the sampling rate of the acquisition system are also getting higher and higher. Due to the restriction of the sampling rate of a single ADC chip, the method of parallel acquisition of multiple ADCs can only be used to improve the system. Sampling Rate. At present, the more popular method is to use time alternate parallel sampling (TIADC) technology to increase the sampling rate of the system, and as the sampling rate increases, the architecture of this type of system presents a complex form of multi-ADC+multi-FPGA. However, due to the complex control of reset signals in this type of multi-device parallel acquisition system, ...

AI Technical Summary

Problems solved by technology

[0006] The traditional method is to use the master-slave method, such as ADC1 as the main chip, reset ADC1 first, transmit the generated synchronous clock to the FPGA, use this synchronous clock to synchronize the reset signal of ADC2, and so on All homologous reset signals are obtained, so that the phase is fixed, but the disadvantage of this approach is that it is greatly affected by the environment. Once the environment changes, the delay change caused by the correction will cause the corrected phase to shift again.

In addition, this master-slave structure will lead to the differentiation of multi-chip FPGAs at the front end of the parallel acquisition system, which increases the complexity of the system and restricts the commercialization of this high-speed acquisition system

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