A mosfet gate oxide capacitance calibration structure

Abstract

The present invention proposes a MOSFET gate oxide layer capacitance calibration structure, comprising: an active region body; a gate located on the active region body; a source and a drain located at both ends of the active region body, And the source and the drain are respectively located on both sides of the gate; the well area is located outside the body of the active area and the gate, and a contact hole is arranged on the well area. The MOSFET gate oxide layer capacitance calibration structure proposed by the present invention retains the active region and the gate polysilicon in the usual MOSFET gate oxide layer capacitance calibration structure, only removes the contact on the source drain and the gate, and can remove the interconnection including the source drain A series of parasitic capacitances including line-to-gate parasitic capacitance, source-drain interconnection line-to-well parasitic capacitance, gate interconnection line-to-well parasitic capacitance, etc., so as to perform more accurate calibration and obtain more accurate MOSFET gate oxidation Layer capacitance simulation model.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a MOSFET gate oxide layer capacitance calibration structure. Background technique [0002] In the prior art, the test structure used to extract the capacitance of the MOSFET gate oxide always includes source-drain contact holes and interconnections, so the measured capacitance of the gate oxide correspondingly includes this part of the parasitic capacitance of the interconnection. In the manufacture of the line width greater than 0.18 microns, the proportion of this part of the interconnection parasitic capacitance is small and is ignored, but in the manufacture of the line width of less than 0.18 microns, the proportion of the interconnection parasitic capacitance is getting larger and larger, and it affects the circuit performance It has a large impact and cannot be ignored. The influence of the source-drain contact hole and interconnection on t...

AI Technical Summary

Problems solved by technology

However, the calibration accuracy of this structure is limited, which brings certain errors to the simulation and later circuit design.

[0004] Therefore, although the commonly used MOSFET gate oxide layer capacitance calibration structure can remove part of the parasitic capacitance, it cannot remove the parasitic capacitance caused by the source-drain interconnection lines, polysilicon and interconnection lines on the gate, resulting in this part of the parasitic capacitance. Remains in the capacitance of the gate oxide layer, so that errors occur in capacitance fitting, resulting in inaccurate device models and affecting circuit design

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