Split capacitor array structure SAR ADC

Abstract

The invention belongs to the field of analog or digital-analogy hybrid integrated circuit technology and relates to a split capacitor array structure SAR ADC. The SAR ADC comprises a high-order capacitor array, a low-order capacitor array and a comparator; the high-order capacitor array and the low-order capacitor array are connected by virtue of one unit capacitor, an upper polar plate of each capacitor of the high-order capacitor array is connected with a sampling switch and performs sampling on an input signal Vin, each upper polar plate is also connected with the input terminal of the comparator, and a lower polar plate of each capacitor of the high-order capacitor array is connected with a voltage reference VREFP or VREFN by virtue of a high-order switch array; and an upper polar plate of each capacitor of the low-order capacitor array is earthed by virtue of an earthing switch SP, and a lower polar plate of each capacitor of the low-order capacitor array is connected with the voltage reference VREFP or VREFN by virtue of a low-order switch array. The SAR ADC provided by the invention improves matching precision of the whole capacitor array, and precision of the SAR ADC is improved.

Description

technical field [0001] The invention belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a SAR ADC with a split capacitor array structure. Background technique [0002] In recent years, with the further improvement of the performance index of the analog-to-digital converter, especially with the continuous development of the integrated circuit process technology, the research on the high-speed asynchronous successive approximation analog-to-digital converter (SAR ADC) has become more and more in-depth. With the continuous evolution of integrated circuit manufacturing processes, the design of high-gain operational amplifiers has become more and more difficult. Since no operational amplifiers are required, SAR ADCs have a natural advantage of low power consumption, especially at nanoscale process nodes. The SAR structure The speed of the ADC has been greatly improved again. Therefore, the high-speed SAR structure ADC has become...

AI Technical Summary

Problems solved by technology

[0008] 1. There may be high voltage in the floating node, causing the breakdown of components and making the circuit invalid;

[0009] 2. There is a parasitic capacitance C between the upper plate of the low-level capacitor array and the ground P2 , this parasitic capacitance and the parasitic capacitance C between the upper plate and the ground of the upper capacitor array P1 There will be a mismatch error, so that there is a mismatch of gain error between the high-position capacitor array and the low-position capacitor array, which will seriously affect the accuracy of the entire SAR ADC;

[0010] 3. In the traditional split capacitor array structure SAR ADC, in order to meet the accuracy, the ideal value of the coupling capacitance between the high capacitor array and the low capacitor array is a value slightly larger than the unit capacitance C ((2 M+1 / 2 M )C), which is difficult to achieve in actual manufacturing, making the SAR ADC in the process of successive approximation from high to low, each weight capacitor switching will introduce errors, and the error introduced by high capacitor array switching will seriously affect the entire SAR ADC accuracy

If the above three problems cannot be solved, it will seriously affect the accuracy of SAR ADC

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