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Hardware circuit implementation method for image matching descriptor generation scale space

A technology of scale space and hardware circuit, applied in computer parts, instruments, characters and pattern recognition, etc., can solve the problems of amazing calculation amount and low operation speed, save processing time, optimize performance, and reduce hardware resource occupancy rate Effect

Inactive Publication Date: 2018-12-07
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For a 512*512 image to generate 3 sets of 6-layer scale spaces, filtering alone requires 6*3=18 sets of filters for convolution operations. Assuming that the average filter template size is 16*16, 512 *512*15*15=2 26 multiplication, the amount of calculation is astonishing;
[0006] 2) Low operation speed

Method used

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  • Hardware circuit implementation method for image matching descriptor generation scale space
  • Hardware circuit implementation method for image matching descriptor generation scale space
  • Hardware circuit implementation method for image matching descriptor generation scale space

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Experimental program
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Embodiment 1

[0040] Such as figure 1 As shown, the present invention provides a hardware circuit implementation method for image matching descriptor generation scale space, including the following steps:

[0041] 1) In a specific application, load the image that needs to be matched, and the specific process is as follows:

[0042] 1.1) read the grayscale floating-point data of the image into DDR through Ethernet;

[0043] 1.2) Read the image data in the DDR into the Buffer sequentially in the order of row first and column second.

[0044] 2) Perform Gaussian smoothing on the image to generate the first group of images, the specific process is:

[0045] 2.1) Using the separability of the Gaussian function, split the two-dimensional Gaussian filter into the convolution of two one-dimensional Gaussian filters, and perform fixed-point processing on the one-dimensional filter template coefficients that need to be used, where the width of the Gaussian template is The size should be proportion...

Embodiment 2

[0079] The scale invariance test of this method is carried out below, and the specific test steps are as follows:

[0080] a) Scale space generation steps of optimizing the source image and the matching image respectively to obtain the respective image scale spaces, that is, the final Gaussian difference pyramid;

[0081] b) The two sets of Gaussian difference pyramids are respectively used to obtain the descriptors of the feature points by the classic SIFT method;

[0082] c) Perform Euclidean distance matching between the matching graph descriptor and the source graph descriptor. The method is: a descriptor whose nearest neighbor distance / second nearest neighbor distance is less than 0.6 is determined as a matching pair, and the number of matching pairs is counted and the time required to complete the matching time consumed.

[0083] By testing the scale invariance of two 640*512 image matching under different platforms and scale space generation methods, Table 1 and Table ...

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Abstract

The invention discloses a hardware circuit implementation method for an image matching descriptor generation scale space. The method comprises a step of loading an image to be matched in a specific application, a step of performing Gaussian smoothing on the image to generate a first group of images, a step of generating a next group of images by using a method of the combination of downsampling and Gaussian filtering, and a step of generating a Difference of Gaussian pyramid according to an obtained Gaussian pyramid. By redesigning a scale space generation method of an SIFT image matching algorithm to adapt to the characteristics of fixed point, parallel and pipeline of an FPGA operation, the speed of scale space generation is accelerated, hardware resources are saved, and therefore, the performance of a whole feature matching module is effectively optimized.

Description

technical field [0001] The invention relates to an image scale space generation method based on the SIFT algorithm family, in particular to a hardware circuit implementation method for image matching descriptor generation scale space. Background technique [0002] At present, image scale space generation is mainly divided into two types: one is multi-scale representation (multi-scale representation), which is based on downsampling and low-pass filtering; the other is scale-space representation (scale-space representation) , using the Laplacian filter at the same sampling rate. The image scale space generation based on the SIFT algorithm family is a combination of the two above methods, taking its advantages and avoiding its shortcomings, and dividing the image scale space into groups (octave) and layers (layer) [1] , so as to form the multi-scale space of the image. [0003] The classic SIFT image scale space generation method is developed on the basis of image multi-scale...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06K9/46
CPCG06V10/462
Inventor 李广朱传杰朱恩邱晓冬朱方杰
Owner SOUTHEAST UNIV
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