3D memory device and manufacture method thereof

Abstract

A 3D memory device and a manufacture method thereof are disclosed. A 3D memory device include a substrate; A laminated structure on the substrate, the laminated structure comprising a plurality of alternately stacked conductor layers and a plurality of insulating layers; A plurality of memory strings running through the laminated structure; An electrically conductive contact extending through thelaminated structure; Wherein the conductive contact is in a polygonal line shape in a first direction perpendicular to the plurality of memory strings. The present invention employs conductive contacts through a laminated structure in a polygonal line shape in a first direction perpendicular to the plurality of memory strings. The conductive contacts extend along the array direction of the memorystrings, thereby reducing the warping deviation of the wafer in a plane perpendicular to the memory strings under a high stack and reducing the distance the metal layer is filled when the conductor layer is formed.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a 3D memory device and a manufacturing method thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] Existing 3D memory devices are mainly used as non-volatile flash memory. The two main non-volatile flash memory technologies use NAND and NOR structures, respectively. Compared with...

AI Technical Summary

Problems solved by technology

[0005] Since the grid line slits all extend along the horizontal direction X, the conductor layers divided by the grid line slits are sequentially arranged along the Y direction perpendicular to the horizontal direction, causing wafer warpage (wafer) after etching the sacrificial layer. warpage) difference; since the gate line gaps are parallel to each other, the filling distance along the Y direction is longer when the tungsten filling is performed after the nitride removal, and the process is more difficult

As the number of stacked layers increases, the warpage difference on the XY plane becomes larger and larger, making the stress distribution uneven

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