Fabrication method of grooved vertical double diffusion metal oxide semiconductor (VDMOS)

A manufacturing method and trench-type technology, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem that trench-type VDMOS cannot work normally, weaken the driving ability of trench-type VDMOS, and reduce trench-type VDMOS cells. Density reduction, etc.

Inactive Publication Date: 2016-11-23
PEKING UNIV FOUNDER GRP CO LTD +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, in this method of implanting P-type ions in the region of the metal contact hole to increase the breakdown voltage, when the bottom of the P-type ion-implantation region 15 is pushed to the depth of the bottom of the second trench 7, the P-type ion-implantation region 15 is also pushed to the bottom of the second trench 7. Diffusion in the lateral direction changes t

Method used

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  • Fabrication method of grooved vertical double diffusion metal oxide semiconductor (VDMOS)
  • Fabrication method of grooved vertical double diffusion metal oxide semiconductor (VDMOS)
  • Fabrication method of grooved vertical double diffusion metal oxide semiconductor (VDMOS)

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Embodiment 1

[0058] Figure 4 It is a flow chart of Embodiment 1 of the trench VDMOS manufacturing method of the present invention, such as Figure 4 As shown, the trench VDMOS manufacturing method provided in this embodiment includes:

[0059] Step 101 , depositing a hard mask layer 3 on the N-type epitaxial layer 2 .

[0060] In this embodiment, the N-type epitaxial layer 2 is grown on the N-type substrate 1 . Wherein, the N-type substrate 1 is a heavily doped N-type substrate, and the N-type epitaxial layer 2 is a lightly doped N-type epitaxial layer. The specific doping concentration of the N-type substrate 1 and the doping concentration of the N-type epitaxial layer 2 are the same as those in the prior art, and will not be repeated here.

[0061] In this embodiment, the hard mask layer 3 deposited on the N-type epitaxial layer 2 may be a silicon dioxide layer. The deposition process may be low pressure chemical vapor deposition. The deposited hard mask layer may have a thickness ...

Embodiment 2

[0095] Figure 18 It is the first flow chart of Embodiment 2 of the trench type VDMOS manufacturing method of the present invention, as Figure 18 As shown, the trench VDMOS manufacturing method provided in this embodiment includes:

[0096] Step 201 , depositing a hard mask layer 3 on the N-type epitaxial layer 2 .

[0097] Step 202 , performing photolithography and etching on the middle region of the hard mask layer 3 to form the first trench window region 4 .

[0098] Step 203 , etching the lower side region of the first trench window region 4 to form a first trench 5 in the N-type epitaxial layer.

[0099] Step 204 , growing P-type epitaxy 6 on the upper surface of the hard mask layer 3 , in the first trench window region 4 and the first trench 5 .

[0100] Step 205, using a chemical mechanical polishing process to remove the P-type epitaxy 6 on the upper surface of the hard mask layer 3, the P-type epitaxy 6 in the hard mask layer 3 and the first trench window region 4...

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Abstract

The invention provides a fabrication method of a grooved vertical double diffusion metal oxide semiconductor (VDMOS). The method comprises the following steps of depositing a hard mask layer on an N-type epitaxial layer; photoetching and etching an intermediate region in the hard mask layer to form a first groove window region; etching a lower-side region of the first groove window region, and forming a first groove in the N-type epitaxial layer; growing P-type epitaxy in an upper surface of the hard mask layer, the first groove window region and the first groove; removing the P-type epitaxy in the upper surface of the hard mask layer, the hard mask layer and the P-type epitaxy in the first groove window region by a chemical mechanical polishing process so as to form a P-type ion region in the first groove; respectively forming second grooves in partial regions at two sides of the P-type ion region in the N-type epitaxial layer; forming a grid oxide layer on an upper surface of the N-type epitaxial layer and a surface in the second groove; depositing a poly-silicon layer on the grid oxide layer in the second grooves; and forming a body region, a source region, a dielectric layer and a metal layer of the grooved VDMOS.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of semiconductor device manufacturing, and in particular, to a method for manufacturing a trench-type VDMOS. Background technique [0002] Trench-type vertical double-diffused metal-oxide-semiconductor transistors (referred to as: trench-type VDMOS) are channeled by forming a vertical diffusion distance difference after source ion and bulk ion implantation, and are widely used in the field of switching power supply and synchronous rectification. Compared with the planar VDMOS, the internal resistance of the trench VDMOS is very small because the JFET area is eliminated. However, due to the small radius of curvature at the corner of the bottom of the trench in the trench VDMOS, the breakdown voltage of the trench VDMOS is relatively low. [0003] In the prior art, in order to increase the breakdown voltage of the trench-type VDMOS, a method of implanting P-type ions into the region of t...

Claims

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Application Information

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IPC IPC(8): H01L21/336
Inventor 闻正锋邱海亮马万里赵文魁
Owner PEKING UNIV FOUNDER GRP CO LTD
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