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OPC correction method for sram layout

A technology of layout and repeating unit, which is applied in the photoengraving process of pattern surface, originals and instruments for opto-mechanical processing, etc. It can solve the problems of long time, inappropriate layout calculation, and complexity.

Active Publication Date: 2022-03-18
SHANGHAI HUALI INTEGRATED CIRCUIT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the pxOPC correction process is extremely complicated and takes a long time. Generally, it is only used to calculate a small part of the screenshot of the layout, and it is not suitable for a complete layout calculation.

Method used

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  • OPC correction method for sram layout
  • OPC correction method for sram layout
  • OPC correction method for sram layout

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0037] Such as Figure 5 As shown, the present invention provides the first embodiment of the OPC correction method of the SRAM layout, comprising the following steps:

[0038] 1) Divide the SRAM layout into a middle area, a transition area and a border area;

[0039] The middle area, the area of ​​repeating cell layout in the SRAM layout;

[0040] The transition area, extending from the boundary of the middle area to the center of the middle area with a preset width, wherein the preset width is greater than 5 to 10 areas of the smallest repeating unit size;

[0041] That is, the predetermined width is greater than 5, 6, 7, 8, 9 or 10 minimum repeating unit sizes. This example extends a distance of 5 minimum repeat unit sizes.

[0042] Boundary area, the remaining area after removing the middle area and transition area in the SRAM layout;

[0043] 2) Perform pxOPC correction on the screenshot of the repeating unit in the SRAM layout to obtain the minimum repeating unit mas...

no. 2 example

[0048] The present invention provides the second embodiment of the OPC correction method of SRAM layout, comprising the following steps:

[0049] 1) Divide the SRAM layout into a middle area, a transition area and a border area;

[0050] The middle area, the area where the smallest repeating unit is laid out in the SRAM layout;

[0051] The transition area, extending from the boundary of the middle area to the center of the middle area with a preset width, wherein the preset width is greater than 5 to 10 areas of the smallest repeating unit size;

[0052] That is, the predetermined width is greater than 5, 6, 7, 8, 9 or 10 minimum repeating unit sizes. This example extends a distance of 10 minimum repeat unit sizes.

[0053] Boundary area, the remaining area after removing the middle area and transition area in the SRAM layout;

[0054] 2) A part of the screenshot containing the repeating unit in the SRAM layout is intercepted for pxOPC correction, and the mask template of th...

no. 3 example

[0060] The present invention provides the third embodiment of the OPC correction method of SRAM layout, comprising the following steps:

[0061] 1) Divide the SRAM layout into a middle area, a transition area and a border area;

[0062] The middle area, the area where the smallest repeating unit is laid out in the SRAM layout;

[0063] The transition area, extending from the boundary of the middle area to the center of the middle area with a preset width, wherein the preset width is greater than 5 to 10 areas of the smallest repeating unit size;

[0064] That is, the predetermined width is greater than 5, 6, 7, 8, 9 or 10 minimum repeating unit sizes. This example extends a distance of 15 minimum repeat unit sizes.

[0065] Boundary area, the remaining area after removing the middle area and transition area in the SRAM layout;

[0066] 2) Take a screenshot of a part of the middle area of ​​the SRAM layout and perform pxOPC correction to obtain the mask of the smallest repea...

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PUM

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Abstract

The invention provides an OPC correction method for the SRAM layout, which divides the SRAM layout into a middle area, a transition area and a boundary area, and corrects the repeating unit screenshot of the SRAM layout through the Caliber pxOPC tool to obtain the mask pattern of the smallest repeating unit of the SRAM , use the Caliber Pattern Match tool to add the mask pattern matching of the smallest repeating unit of SRAM to the middle area of ​​the SRAM layout, and then perform OPC correction on the transition area and boundary area of ​​the SRAM layout to obtain the final mask layer of the SRAM layout. This method can greatly reduce the OPC operation time, and ensures the consistency of the size of the mask plate in the repeated unit area in the middle of the SRAM layout.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to an OPC (Optical Proximity Effect Correction) correction method for an SRAM layout with a critical dimension of 22nm or below. Background technique [0002] With the development of semiconductor technology, the key dimensions of devices are getting smaller and smaller. When the process node reaches 16 nanometers or 14 nanometers and below, the method of splitting a layer of layout into multiple layers and performing multiple exposures by photolithography is generally used. It is used to solve the limitation that the wavelength of the light source of DUV lithography machine reaches the limit. When the process node is 20nm or 22nm, the OPC correction of the layout without multi-layer splitting is unprecedentedly difficult. The line width and spacing in the layout are the limit values ​​that the machine can bear, so OPC The difficulty is very huge. [0003] The pxOPC product of Calibe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F1/36
CPCG03F1/36
Inventor 陈燕鹏赵璇于世瑞
Owner SHANGHAI HUALI INTEGRATED CIRCUIT CORP