Preparation method of iii-vhemt device with thermoelectric power generation mechanism
A technology of III-VHEMT and thermoelectric power generation, applied in the field of preparation of III-VHEMT devices, can solve problems such as energy waste, and achieve the effects of improving efficiency, reducing energy loss and saving energy
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[0032] A preparation method of a III-VHEMT device with a thermoelectric power generation mechanism of the present invention is characterized in that the method specifically comprises the following steps:
[0033] As shown in Figure 2(a)-(l),
[0034] Step (a) forming a second semiconductor layer 5 and a first semiconductor layer 4 on the selected substrate 101 and buffer layer 102 and forming a heterostructure between the second semiconductor layer 5 and the first semiconductor layer 4, and A two-dimensional electron gas (2DEG) 12 is formed on the side of the second semiconductor 5 at the interface of the heterostructure;
[0035] Step (b) performing ion implantation isolation on the first semiconductor layer 4 to define the active area of the device, in the active area, 2DEG is retained, and in the non-active area, 2DEG is depleted by ion implantation;
[0036] Step (c) making a source electrode 1 and a drain electrode 3 on the first semiconductor 4; the source electrode 1...
Embodiment 1
[0048] The device of this embodiment includes a source 1, a gate 2, a drain 3, a first semiconductor layer 4, a second semiconductor layer 5 located on the lower surface of the first semiconductor layer 4, a first semiconductor layer located on the lower surface of the second semiconductor layer Metal layer 6, N-type thermoelectric material 7 and P-type thermoelectric material 8 located on the lower surface of the first metal layer 6, second metal layer 9 located on the lower surface of the N-type thermoelectric material N-type thermoelectric material 7, located on the P-type thermoelectric material 8 The third metal layer 10 on the lower surface, the heat dissipation layer 11 located on the lower surface of the second metal 9 and the third metal layer 10 . The source 1 , the gate 2 and the drain 3 are all arranged on the upper surface of the first semiconductor layer 4 , and the gate 2 is located between the source 1 and the drain 3 . The lower surface of the first metal laye...
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