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A successive approximation analog-to-digital converter and a low power switching algorithm thereof

An analog-to-digital converter, successive approximation technology, applied in the direction of analog/digital conversion, code conversion, instrument, etc., can solve the problems of power consumption and large occupied area, so as to simplify the design, save the chip area, reduce the switch Toggle the effect of energy consumption

Active Publication Date: 2018-12-18
SOUTHEAST UNIV
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Problems solved by technology

The traditional switching algorithm will make the power consumption and area occupied by the capacitor array larger, which is not conducive to the wide application in the current low power consumption field

Method used

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  • A successive approximation analog-to-digital converter and a low power switching algorithm thereof
  • A successive approximation analog-to-digital converter and a low power switching algorithm thereof
  • A successive approximation analog-to-digital converter and a low power switching algorithm thereof

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Embodiment Construction

[0051] The present invention will be further described below in conjunction with the accompanying drawings.

[0052] figure 1 Shown is a successive approximation analog-to-digital converter structure using upper plate sampling technique.

[0053] figure 1 The capacitor array shown can realize the conversion of N-bit SARADC. The entire capacitor is divided into identical upper and lower capacitor arrays. Each capacitor array mainly includes a dummy capacitor C d , the lowest bit capacitance C u and the highest bit capacitance C N-3 , other capacitors are allocated according to binary weights, specifically:

[0054] ①The highest capacitance C N-3

[0055] Highest capacitance C N-3 splits into the exact same structure as all other low-position capacitive structures, namely C N-3 Numerically equal to the sum of all other low capacitances, the expression is:

[0056] C N-3 =C D +C 0 +C 1 +C 2 +…+C N-4 = 2 N-3 C u

[0057] ②The lowest capacitance C 0 To the second...

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Abstract

The invention discloses a successive approximation type analog-to-digital converter and a low power consumption switching algorithm thereof. By adopting a split capacitor array structure and a reasonable control logic setting, the energy consumed by the capacitor array in the switching process of the SAR ADC is greatly reduced. Compared with the traditional switching algorithm, the switching algorithm of the invention saves 99.76% of the conversion energy and 75% of the capacitor area, and improves the economic benefit. In addition, the switching algorithm provided by the invention makes the output common-mode voltage of the capacitor array only change slightly when the lowest bit is converted, thereby greatly reducing the design complexity of the comparator.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a successive approximation analog-to-digital converter structure and a low-power switching algorithm using upper plate sampling technology. Background technique [0002] Successive approximation analog-to-digital converters (SARADC) are widely used in low-power applications such as wireless sensor nodes, biomedical electronics, and environmental monitoring. SARADC is mainly composed of capacitor array, comparator and digital control logic. Among them, the power consumption of the digital control logic is continuously reduced with the progress of the process size, and the use of the dynamic comparator also makes the proportion of the power consumption of the comparator in the power consumption of the SARADC smaller and smaller. The traditional switching algorithm will consume a large amount of power consumption and area occupied by the capacitor array, whi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/00H03M1/46
CPCH03M1/002H03M1/466
Inventor 吴建辉王甫锋王鹏包天罡李红
Owner SOUTHEAST UNIV
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