Super junction MOS power semiconductor device and preparation method thereof
A technology of power semiconductors and semiconductors, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems that the drift region cannot be completely exhausted, reduce the on-resistance, etc.
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Embodiment 1
[0103] This embodiment provides a super junction LDMOS device, the cell structure of which is as follows figure 2 as shown, figure 2 The schematic diagrams of the cross-sectional structure of the cellular structure along the AB line and the CD line are shown in Fig. image 3 with 4 As shown, the cellular structure of the superjunction LDMOS device includes a bottom-up substrate electrode 15, a substrate, an N-type buffer layer 12, and an N-type drift region 10; one side of the surface of the N-type drift region 10 has a trench gate structure , the trench gate structure includes a trench gate electrode 1 and a trench gate dielectric layer 2 on its side and bottom surface; the other side of the surface of the N-type drift region 10 has an N-type drain region 9, and the upper surface of the N-type drain region 9 has a metal There is a deep dielectric trench 4 in the N-type drift region 10 between the trench gate structure and the N-type drain region 9, and the top layer of th...
Embodiment 2
[0107] This embodiment provides a super junction LDMOS device, the cell structure of which is as follows Figure 5 as shown, Figure 5 The schematic diagrams of the cross-sectional structure of the cellular structure along the AB line and the CD line are shown in Fig. Image 6 with 7 shown. In this embodiment, on the basis of Embodiment 1, a first field plate 401 and a second field plate 402 are introduced into the deep dielectric trench 4 along the direction in which the N-type pillar regions 10 and the P-type pillar regions 11 are alternately arranged. The longitudinal depths of the first field plate 401 and the second field plate 402 are smaller than the longitudinal depth of the deep dielectric trench 4 . The thickness of the dielectric layer between the first field plate 401 and the second field plate 402 and the edge of the deep dielectric trench 4 can be adjusted, that is, a field plate with a uniform dielectric layer thickness can be used, a stepped field plate can ...
Embodiment 3
[0110] This embodiment provides a super junction LDMOS device, the cell structure of which is as follows Figure 8 as shown, Figure 8 The schematic diagrams of the cross-sectional structure of the cellular structure along the AB line and the CD line are shown in Fig. Figure 9 with 10 As shown, this embodiment is based on Embodiment 1. In the N-type drift region 10 below the N-type drain region 9, a side N-type buffer layer 16 close to the side wall of the deep dielectric trench 4 is also provided. The doping concentration of the N-type buffer layer 16 is not less than the doping concentration of the N-pillar 10 . The doping concentration of the side N-type buffer layer 16 can be uniformly doped, or can be gradually decreased from top to bottom.
[0111] The introduction of the side N-type buffer layer 16 can suppress the impact of auxiliary depletion on the charge balance of the superjunction structure caused by the difference in potential on both sides of the deep trench...
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Abstract
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