A fast placement method for large-scale ultra-sparse planar arrays with controllable minimum pitch

A planar array and layout method technology, which is applied in antenna arrays, complex mathematical operations, antennas, etc., can solve the problems of sparse layout and high complexity that cannot be applied to large-scale planar arrays, and achieve the effect of reducing array fill factor and rapid layout

Active Publication Date: 2019-01-15
XIAMEN UNIV +1
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Problems solved by technology

However, this method needs to use a convex optimization algorithm in each iteration process, its complexity is much higher than the FFT-based array layout algorithm, and it cannot be applied to the sparse layout of large-scale planar arrays

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  • A fast placement method for large-scale ultra-sparse planar arrays with controllable minimum pitch
  • A fast placement method for large-scale ultra-sparse planar arrays with controllable minimum pitch
  • A fast placement method for large-scale ultra-sparse planar arrays with controllable minimum pitch

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[0068] The following is attached Figure 1-7 The preferred embodiments of the present invention are described, and it should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0069] Design goal: at 3GHz frequency, at 3GHz frequency, the array size is 50λ×50λ, (if the half-wavelength is used as the spacing, the number of full arrays is 100×100), the array is required to be arranged within a circular outline, and the minimum spacing is constrained 0.5 times the wavelength, the peak level of the side lobe area is not higher than -25dB.

[0070] The specific implementation steps are as follows:

[0071] a) Take the grid density as Δ=λ / 4, that is, set the grid at intervals of 1 / 4 wavelength. At this time, the number of full arrays is M×N (if the grid is used as the interval, the number of full arrays is 200×200) , the array element spacing constraint is ...

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Abstract

The invention discloses a large-scale ultra-sparse plane array rapid layout method with controllable minimum pitch, the layout method is divided into two steps: initial optimization with unlimited minimum spacing and correction optimization with limited minimum spacing. S01: in the initial optimization, array layout with dense grid is adopted, array element excitation is randomly initialized, anda fast synthesis array optimization algorithm with grid spacing not equal to half wavelength is proposed, i.e., iterative Chirp-Iterative Chirp-z transform (ICZT); on this basis, the improved ICZT isproposed to synthesize low sidelobe level, and the concept of filling factor is introduced to reduce the number of array elements gradually to achieve the purpose of sparse array, and the condition ofiteration termination is improved to obtain the array layout with the lowest sparse rate as far as possible. S02: in the correction optimization, the concept of discarding exponent is proposed, and the array element is discarded to satisfy the constraint of array element spacing. The invention completes the fast layout of a large-scale ultra-sparse planar array with controllable minimum pitch.

Description

technical field [0001] The invention relates to a rapid layout method of a large-scale ultra-sparse planar array with controllable minimum spacing, and belongs to the technical field of antennas. Background technique [0002] In recent years, antenna array synthesis has been widely used in radar, communication, electronic countermeasure technology and other fields. Compared with the full array of the same caliber, although the sparse array has a certain gain loss, its advantages are obvious, and there are three main ones: First, the number of array elements is reduced on the basis of obtaining an approximate beam width of the full array, which reduces the cost of the array. The cost and weight of the system; the second is that the average spacing of the sparse part increases, which can reduce the influence of the mutual coupling of the array and reduce the heat dissipation complexity of the array system; sidelobe level. Based on the above characteristics, array sparseness ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50G06F17/14H01Q21/00
CPCH01Q21/00G06F17/142G06F30/392Y02D30/70
Inventor 刘颜回罗阡珂徐开达叶龙芳刘海
Owner XIAMEN UNIV
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