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Analog-digital-combined low-frequency phase-locked loop

An analog-digital combination, phase-locked loop technology, applied in the direction of automatic power control, electrical components, etc., can solve the problems of poor analog phase-locked loop stability, complex technology, long phase-locking time, etc., to improve stability and reaction efficiency. , the effect of reducing technical difficulty

Pending Publication Date: 2019-02-22
佛山市秀声电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In order to solve the problems of high cost, complex technology and poor stability of analog phase-locked loops and long phase-locked time of existing digital phase-locked loops, a new phase-locked loop combining analog and digital is provided

Method used

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  • Analog-digital-combined low-frequency phase-locked loop
  • Analog-digital-combined low-frequency phase-locked loop
  • Analog-digital-combined low-frequency phase-locked loop

Examples

Experimental program
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Embodiment 1

[0016] Embodiment 1: This embodiment provides a low-frequency phase-locked loop combining modulus, such as Figure 1-3 As shown, it includes a digital processing module and an analog circuit module, the digital processing module includes a digital phase detector 1 and a frequency divider 2, and the input of the digital phase detector 1 is respectively connected to the output of the frequency divider 2 and the external Reference clock signal; Described analog circuit module comprises low-pass filter 4, low-frequency voltage-controlled oscillator 5 and the three-state bus buffer 3 that pulse signal is converted into voltage signal, the input terminal of described tri-state bus buffer 3 and The enabling end is respectively connected with the two output ends of the digital phase detector 1, the input end of the low-pass filter 4 is connected with the output end of the three-state bus buffer 3, and the output end of the low-pass filter 4 is connected with the low-frequency voltage ...

Embodiment 2

[0017] Embodiment two: on the basis of embodiment one, digital phase detector 1 and frequency divider 2 are integrated in FPGA or CPLD, and digital phase detector 1 and frequency divider 2 are packaged together; Adopt four D digital frequency discrimination The phase detector is used as the digital phase detector 1, and the frequency divider 2 is a variable frequency divider. Integrated digital phase detector 1 and frequency divider 2 can save space, and real-time editing FPGA or CPLD can perform multiple processing on signals.

Embodiment 3

[0018] Embodiment 3: On the basis of Embodiment 1, the low-pass filter 4 is a second-order low-pass filter formed by connecting two RC filters in series, and the analog signal obtained after the second-order filtering is smoother.

[0019] The present invention has the advantage of being easy to implement, adopts digital logic chip to add analog circuit and can realize; The input terminals are respectively connected to the frequency divider 2 and the reference clock signal. The internal logic of the digital phase detector 1 is similar to a four-D phase detector. It compares the two input signals and outputs two output pulses with different phases and frequencies. signal, the frequency difference and phase difference of the input pulse signal are positively correlated with the duty cycle of the output pulse signal. The three-state bus buffer 3 will output continuous voltage signals with different amplitudes according to the duty cycle of the output pulse signal, and the voltage...

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Abstract

The invention relates to the technical field of phase-locked loops, in particular to a novel analog-digital hybrid combined low-frequency phase-locked loop, which comprises a digital processing moduleand an analog circuit module, wherein the digital processing module comprises a digital phase discriminator and a frequency divider; the analog circuit module comprises a tristate bus buffer, a low-pass filter and a low-frequency voltage-controlled oscillator which are electrically connected in sequence; the input end of the digital phase discriminator is connected to the output end of the frequency divider and an external reference clock signal respectively; and the low-frequency voltage-controlled oscillator is electrically connected to the input end of the frequency divider to form a frequency feedback loop. According to the method disclosed by the invention, phase discrimination is carried out through a digital technology and phase locking is carried out through combination with the analog circuit, so that the stability and the reaction efficiency of the phase-locked loop are improved; and compared with a digital phase-locked loop, the technical difficulty and the overall cost arereduced.

Description

technical field [0001] The invention relates to the technical field of phase-locked loops, in particular to a low-frequency phase-locked loop with combination of modulus and digital. Background technique [0002] A phase-locked loop is a feedback circuit (PLL). Its working principle is to detect the phase difference between the input signal and the output signal, and convert the detected phase difference signal into a voltage signal output through a phase detector. After filtering by a low-pass filter The control voltage of the voltage-controlled oscillator is formed, the frequency of the oscillator output signal is controlled, and then the frequency and phase of the oscillator output signal are fed back to the phase detector through the feedback path. During the working process of the phase-locked loop, when the frequency of the output signal reflects the frequency of the input signal in proportion, the output voltage and the input voltage maintain a fixed phase difference,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/087H03L7/10
CPCH03L7/087H03L7/10
Inventor 卓严亮
Owner 佛山市秀声电子科技有限公司