Method and device for automatically repairing the bit line fault of a NOR type memory array

Abstract

The embodiment of the invention provides a method and device for automatically repairing the bit line fault of a NOR type memory array. The method comprises the following steps: testing the bit line current on each bit line in the memory array; if the bit line current is negative, marking the bit line as the fault bit line, and recording the address of the memory cell on the fault bit line; if thebit line current is negative, marking the bit line as the fault bit line. The mapping relationship between the memory cells on the fault bit line and the memory cells in the redundant column is established. A method and device for automatically repairing the word line faults of a NOR-type memory array are provide in embodiments of that present invention, The fault bit line is confirmed by the bitline current of each bit line in the memory array, and the mapping relationship between the memory cells included in the fault bit line and the memory cells in the redundant column is established, sothat the memory cells included in the bit line fault are repaired, the test overhead is reduced, and the yield and reliability of the memory array are improved.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of non-volatile memory, and in particular, to a method and device for automatically repairing bit line faults in a NOR memory array. Background technique [0002] In a NOR-type memory array composed of a floating gate FET as a memory cell, the signal that controls the voltage at the gate terminal is called a word line, and the signal that controls the voltage at the drain terminal is called a bit line. In the process of practical application, on the one hand, with the development of semiconductor technology, the area of ​​the unit storage cell is getting smaller and smaller, and the bit line and the active area are connected by via holes, and the hole punching process is very easy in the manufacturing process. bias. On the other hand, multiple programming and erasing operations can cause defects in the isolation layer between word lines and bit lines. Due to the deviation of the proce...

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Problems solved by technology

[0003] In the prior art, after the problem of a short circuit between the bit line and the word line, the method adopted is to directly discard all the memory cells contained on this bit line, so that the memory cells available for storage in the entire memory array become more and more less, so it's not a good way to

Or in the prior art, an external device is often used for redundancy analysis, and then the storage array is repaired by using an external laser device to modify the setting of the fuse box of the storage array, and the external device is used for fault diagnosis and redundant resource analysis of the storage array. to a larger expense

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