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Semiconductor structure with character line and making method thereof

A manufacturing method and word line technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc.

Active Publication Date: 2019-03-22
UNITED MICROELECTRONICS CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, there are still some problems with the existing trench gate

Method used

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  • Semiconductor structure with character line and making method thereof
  • Semiconductor structure with character line and making method thereof
  • Semiconductor structure with character line and making method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] Figure 1 to Figure 12 A method for fabricating a semiconductor structure with word lines is illustrated according to a preferred embodiment of the present invention. see figure 1 and figure 2 . figure 1 for the top view, figure 2 is along figure 1 Side view of A-A' tangent direction and B-B' tangent direction in middle. First provide a substrate 10, the substrate can be a silicon (Silicon) substrate, a germanium (Germanium) substrate, a gallium arsenide (Gallium Arsenide) substrate or a silicon germanium (Silicon Germanium) substrate, the substrate 10 is preferred in the present invention for the silicon substrate. The substrate 10 is divided into a memory area A and a peripheral element area B, a first trench 12 and a second trench 14 are formed in the substrate 10 in the memory area A, and a first trench 12 and a second trench 14 are formed in the substrate 10 in the peripheral element area B. The third trench 16, the first trench 12 and the second trench ...

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PUM

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Abstract

The invention discloses a semiconductor structure with a character line and a making method thereof. The semiconductor structure with a character line includes a substrate consisting of a memory areaand a peripheral component area, a first groove and a second groove arranged in the memory area, a third groove arranged in the peripheral component area, a first silicon oxide layer arranged in the lower half of the first groove, a silicon nitride layer filling the second groove and the third groove, a third silicon oxide layer arranged in the third groove, and a character line filling the upperhalf of the first groove and covering the silicon nitride layer in the second groove, wherein the width of the first groove, the second groove and the third groove increases in turn, and the upper surface of the silicon nitride layer in the second groove overlapping the character line is not lower than the upper surface of the first silicon oxide layer overlapping the character line.

Description

technical field [0001] The invention relates to a semiconductor structure with word lines and a manufacturing method thereof, in particular to a semiconductor structure with word lines capable of reducing parasitic capacitance and a manufacturing method thereof. Background technique [0002] Dynamic random access memory (dynamic random access memory, DRAM) is a kind of volatile memory, including a memory cell region composed of multiple memory cells and a peripheral component region composed of control circuits. area). Each memory cell includes a transistor electrically connected to a capacitor, and the transistor controls the storage or release of charges in the capacitor to achieve the purpose of storing data. The control circuit can locate each memory cell to control its data access by using a word line (WL) and a bit line (BL) across the memory area and electrically connected to each memory cell. [0003] With the evolution of manufacturing technology generations, in o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/108H01L21/8242H10B12/00
CPCH10B12/37H10B12/488H01L29/0653H10B12/34H10B12/09H01L21/31111
Inventor 张峰溢李甫哲
Owner UNITED MICROELECTRONICS CORP