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Method and test system for locating memory failure bits based on soc ATE

A technology for testing systems and failure bits, applied in static memory, instruments, etc., can solve problems such as inability to conveniently read memory failure bit information, and achieve the effects of improving test efficiency, shortening test time, and improving efficiency

Active Publication Date: 2020-10-09
SHANGHAI HUALI INTEGRATED CIRCUIT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0016] The technical problem to be solved by the present invention is to provide a method and a test system for locating memory failure bits based on SOC ATE, which can solve the problem that the memory failure bit information cannot be easily read when the existing vector mode of SOC ATE is used for memory testing

Method used

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  • Method and test system for locating memory failure bits based on soc ATE
  • Method and test system for locating memory failure bits based on soc ATE
  • Method and test system for locating memory failure bits based on soc ATE

Examples

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no. 1 example

[0055] The test system based on the SOC ATE location memory failure bit of the present invention comprises:

[0056] A test vector generation module is used to generate test vectors;

[0057] A waveform conversion module, which is used to convert the test vector output by the test vector generation module into a physical waveform signal;

[0058] The drive module is used to apply the physical waveform signal as an excitation to the chip to be tested and store the collected test results (that is, the pin pass-fail information) into the RAM in the form of characters, and output each failure from the RAM at the same time. The data pin state and the corresponding address pin state of the failure bit pointed to by the vector;

[0059] The data structure construction module is used to respectively construct the corresponding relationship between the data in character form and the data in numerical form for the pin type (ie address pin and data pin);

[0060] The data conversion mo...

no. 2 example

[0071] In this embodiment, the test system for locating memory failure bits based on SOC ATE includes:

[0072] A test vector generation module is used to generate test vectors;

[0073] A waveform conversion module, which is used to convert the test vector output by the test vector generation module into a physical waveform signal;

[0074] The drive module is used to apply the physical waveform signal as an excitation to the chip to be tested and store the collected test results (that is, the pin pass-fail information) into the RAM in the form of characters, and output each failure from the RAM at the same time. The data pin state and the corresponding address pin state of the failure bit pointed to by the vector;

[0075] The data structure construction module is used for respectively constructing the corresponding relationship between character form data and numerical form data according to the pin type, wherein the numerical form data adopts binary data;

[0076] The da...

no. 3 example

[0089] In this embodiment, the test system for locating memory failure bits based on SOC ATE includes:

[0090] A test vector generation module is used to generate test vectors;

[0091] A waveform conversion module, which is used to convert the test vector output by the test vector generation module into a physical waveform signal;

[0092] The drive module is used to apply the physical waveform signal as an excitation to the chip to be tested and store the collected test results (that is, the pin pass-fail information) into the RAM in the form of characters, and output each failure from the RAM at the same time. The data pin state and the corresponding address pin state of the failure bit pointed to by the vector;

[0093] The data structure construction module is used to respectively construct the corresponding relationship between the pin state represented by characters and the pin state represented by numerical value according to the pin type, wherein the numerical value...

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Abstract

The invention discloses a method and a test system for positioning a memory failure bit based on SOC ATE. The method comprises the following steps: generating a test vector; Converting the test vectorinto a physical waveform signal; Inputting the physical waveform signal into a chip to be tested for testing; Storing a test result (pin pass-fail information) into the RAM in a character form according to lines; The ATE reads the data pin state of the failure bit indicated by each failure vector and the corresponding address pin state from the RAM; Constructing a corresponding relationship between the pin state represented by the character and the pin state represented by the numerical value; And converting the address pin state and the data pin state of each failure bit into numerical formsfrom a character form and outputting the numerical forms. On the basis that hardware resources are not increased, the character data obtained through the vector mode test based on the SOC ATE are rapidly converted into the numerical data, failure positioning and failure analysis are conveniently conducted on the memorizer, and the efficiency of developing a memorizer test program through the SOCATE is improved.

Description

technical field [0001] The invention relates to the field of microelectronics and semiconductor integrated circuit manufacturing, in particular to memory testing technology, in particular to a method and a testing system for locating memory failure bits based on SOC ATE. Background technique [0002] The memory (Memory) has a simple and symmetrical structure, and is used to store or temporarily store the data and calculation results involved in the calculation, and has been widely used in electronic communication products. With the development of integrated circuit design technology, more and more memories have been embedded or plugged into ASIC chips and FPGA chips for use. [0003] However, memory often has some failures, such as incorrect memory read and write functions or data in one memory is affected by data or read and write operations in other memories. Therefore, before mass production and during the development of new memories, memory It is very important to condu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/56
CPCG11C29/56
Inventor 舒颖李强郑鹏飞
Owner SHANGHAI HUALI INTEGRATED CIRCUIT CORP