How the transistor is formed
A transistor and gas atmosphere technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems affecting transistor performance, and achieve the effect of improving performance and reducing parasitic capacitance
Active Publication Date: 2022-03-25
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0005] However, in practical applications, it is found that the gate 2, the stress layer 5, and the outer wall 3 between the gate 2 and the stress layer 5 will form a relatively high parasitic capacitance, thereby affecting the performance of the transistor
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[0035] As mentioned above, the gate of the existing transistor, the embedded stressor layer serving as the source electrode and the drain electrode, and the outer wall between the gate electrode and the stressor layer will form a large parasitic capacitance, which affects the performance of the transistor.
[0036] continue to refer to figure 1 , after research, it is found that the reason for the large parasitic capacitance is that the outer wall 3 uses silicon nitride with a large dielectric constant, and the reason for using silicon nitride is that it can be etched to make silicon A sigma-type groove 4 is formed therein.
[0037] In view of the above reasons, the present invention provides an improved solution, which firstly forms an outer sacrificial spacer around the area where the gate is to be formed, and then replaces the outer sacrificial spacer with a larger dielectric constant with a smaller dielectric constant. In this way, the gate, part of the gate, part of the ...
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Abstract
The present invention provides a method for forming a transistor, which includes: providing a substrate; forming an outer sacrificial spacer around the area where the gate of the transistor is to be formed; forming a groove; removing the outer sacrificial spacer, forming an outer sidewall around the area where the gate is to be formed, the dielectric constant of the outer sidewall is smaller than the dielectric constant of the outer sacrificial sidewall; forming a source electrode . A stress layer of the drain, the stress layer is at least partially located within the groove. By replacing the outer sacrificial spacer with a higher dielectric constant with the outer wall with a lower dielectric constant, the gate, the stress layer as the source and drain, and the parasitic capacitance formed by the outer wall around the gate can be reduced. Small, improves the performance of the transistor.
Description
technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a method for forming a transistor. Background technique [0002] With the continuous development of semiconductor technology, carrier mobility enhancement technology has been widely studied and applied. Improving the carrier mobility in the channel region can increase the driving current of MOS devices and improve device performance. [0003] In the existing semiconductor device fabrication process, since stress can change the energy gap and carrier mobility of silicon materials, it has become more and more common to improve the performance of MOS transistors by embedding stress layers. Specifically, by properly controlling the stress, the mobility of carriers (electrons in NMOS transistors, holes in PMOS transistors) can be improved, thereby increasing driving current, thereby greatly improving the performance of MOS transistors. [0004] like figure 1 As s...
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IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/6656H01L29/66636H01L29/7848
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP