A fpga dynamic phase adjustment method applied to ad source synchronous data reception
An adjustment method and a dynamic phase technology, applied in the direction of pulse shaping, multiplexing communication, single output arrangement, etc., can solve the problem that the double-edge data rate is lower than 400Mbps source synchronous data receiving application requirements, etc., to reduce the lower limit Requirements, the effect of overcoming transmission errors
Active Publication Date: 2020-07-31
XI'AN INST OF OPTICS & FINE MECHANICS - CHINESE ACAD OF SCI
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[0005] In order to overcome the problem that the existing dynamic phase adjustment (DPA) method based on XILINX company FPGA cannot meet the application requirements of double edge data rate lower than 400Mbps source synchronous data reception, the present invention provides a kind of FPGA dynamic phase adjustment applied to AD source synchronous data reception. Phase adjustment method
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[0040] Attached below Figure 1-2 The present invention is further described.
[0041] Utilize the principle block diagram of the present invention to receive AD source synchronous data as figure 1 As shown, the source synchronous clocks Clk_lvds_p and Clk_lvds_n are converted from differential to single-ended through IBUFDS (IBUFDS is an internal function module of FPGA, which can be directly called, and used to convert differential clock to single-ended clock), and then pass through BUFIO and BUFR respectively: BUFIO output clock Drive the IO logic resource ISERDES; BUFR divides by four to generate the clock signal clkdiv, and the signal clkdiv drives the internal logic of the FPGA such as the ISERDES module (ISERDES_master, ISERDES_slave), DPA and Bitslip.
[0042] AD source synchronous data (Data_lvds_p and Data_lvds_n) first pass through IBUFDS, and then access the ISERDES module. The ISERDES module integrates IDELAY and serial-to-parallel units. Two ISERDES modules ar...
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An existing dynamic phase adjustment (DPA) method based on XILINX company FPGA can not be used to satisfy an application requirement that a bilateral edge data rate is lower than 400Mbps source synchronization data receiving. In order to overcome the above problem, the invention provides an FPGA dynamic phase adjustment method applied to AD source synchronization data receiving. The method comprises the following steps of 1) initializing AD by the FPGA; 2) configuring AD work in a training mode and outputting a training word; 3) receiving serial data output by the AD and converting to paralleldata; 4) carrying out DPA adjusting; and 5) carrying out BITSLIP adjustment. In a DPA adjustment link, prior information is fully used, which means that an AD source synchronization data frequency isknown, the rising edge of serial data stream high and low level changes is only searched, an IDELAY optimal delay coefficient is obtained by calculation, and a DPA process is simplified. Because therising edge of serial data stream high and low level changes is only searched, the delay needs to cover the width of 1 bit data at most, and a DPA data rate can be greater than 203 MHz. The lower limit requirement of an existing DPA method to a data rate is reduced, and the application requirement of the source synchronization data receiving with the data rate which is lower than 400 Mbps can be satisfied.
Description
technical field [0001] The invention relates to the field of high-speed data transmission, in particular to an FPGA dynamic phase adjustment method applied to AD source synchronous data reception. Background technique [0002] AD source synchronous data reception includes clock signal and data signal, the signal frequency is high, usually double-edge differential serial data. The serial data of AD determines the serial-to-parallel conversion sequence through the training word. [0003] As the data transmission rate increases, the clock’s hold time for data sampling narrows, that is, the sampling accuracy decreases, and due to the different transmission paths, the delay of the signal reaching the receiving end cannot be guaranteed to be exactly the same, that is, the clock has deviations in the sampling of multiple channels of data. . To this end, static phasing as well as dynamic phasing occurs. Static phase adjustment SPA makes the delay of each signal on its transmissio...
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IPC IPC(8): H03K5/14H03K3/02H03K5/01H04J3/06
CPCH03K3/02H03K5/01H03K5/14H04J3/0617
Inventor 魏文鹏陈小来温志刚石兴春刘强张昕
Owner XI'AN INST OF OPTICS & FINE MECHANICS - CHINESE ACAD OF SCI