Software and hardware partitioning method for a dynamic part reconfigurable system-on-chip

A technology of software and hardware division and dynamic part, which is applied to digital computer components, architecture with a single central processing unit, instruments, etc., can solve the problems of local optimal solution existing model complexity, too large, etc., and achieve guaranteed matching Degree, reduce complexity, improve the effect of solving speed

Active Publication Date: 2019-04-19
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

[0005] In order to overcome the shortcomings that random optimization algorithms are easy to fall into local optimal solutions and existing models are too complex, the present invention provides a method for partitioning software and hardware of dynamic partially reconfigurable SoCs

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  • Software and hardware partitioning method for a dynamic part reconfigurable system-on-chip
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  • Software and hardware partitioning method for a dynamic part reconfigurable system-on-chip

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Embodiment Construction

[0057] The present invention will be further described below in conjunction with accompanying drawing:

[0058] figure 1 is the SoC heterogeneous system targeted by the present invention. like figure 1 As shown, the heterogeneous system-on-chip integrates CPU and field-programmable gate array (FPGA), and the FPGA in this system has the characteristic of dynamic partial reconfiguration. The FPGA programmable logic unit in the system can be divided into several partially reconfigurable areas, such as PR0 and PR1 in the figure, each reconfigurable area can realize functional reconfiguration by downloading different configuration files through ICAP / PCAP according to actual needs;

[0059] figure 2 It is the software and hardware division process described in 1.2.

[0060] To sum up, the efficient MILP model proposed by the present invention speeds up the problem-solving speed by reducing the complexity of variables and constraint equations, and can provide developers of dynam...

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Abstract

The invention relates to a software and hardware partitioning method for a dynamic part reconfigurable system-on-chip. The problems of task mapping, task sequencing, task scheduling, task reconstruction sequencing, inter-task communication and the like in the software and hardware partitioning problem can be solved. According to the method, a software and hardware division problem is described asa refined mathematical model, so that an optimal solution can be obtained by adopting a solver with less time complexity. Meanwhile, according to the method disclosed by the invention, the reconstruction time of all tasks allocated to the reconfigurable area of the FPGA dynamic part is taken into consideration, so that the coincidence degree of the result and the actual application is improved, and the method has higher application value.

Description

technical field [0001] The invention relates to the cooperative design of software and hardware of a dynamically partially reconfigurable system-on-chip, in particular to the software-hardware division problem in a system-on-chip based on a microprocessor and a dynamically partially reconfigurable programmable logic gate array. Background technique [0002] With the development of technology, people have higher and higher requirements on the processing power of computing systems. 5G, high-definition multimedia, artificial intelligence, etc. all require high-performance computing systems to support them. However, the chip manufacturing process has reached the limit of 7nm, which makes the traditional method of improving processor performance by increasing the number of components on the integrated circuit encounter a bottleneck; therefore, reconfigurable system-on-chip (SoC) has attracted the attention of the industry. Among them, a system-on-chip integrating a microprocesso...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78
CPCG06F15/7807G06F15/7867
Inventor 唐麒魏急波朱丽花周力辜方林王杉熊俊
Owner NAT UNIV OF DEFENSE TECH
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