An FPGA-based domestic platform database acceleration system and method

A technology for accelerating systems and databases, applied in database design/maintenance, structured data retrieval, architecture with a single central processing unit, etc., can solve problems such as high CPU power consumption, non-openness, and limited performance of independent CPUs, and achieve outstanding results Substantial features, reliable design principles, and the effect of improving execution efficiency

Pending Publication Date: 2019-05-10
SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

CPU power consumption is high, CPU can only do data parallelism, not pipeline parallelism
The independent CPU has limited performance, does not support gener

Method used

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  • An FPGA-based domestic platform database acceleration system and method
  • An FPGA-based domestic platform database acceleration system and method
  • An FPGA-based domestic platform database acceleration system and method

Examples

Experimental program
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Embodiment 1

[0045] Such as Figure 1-2 As shown, a domestic platform database acceleration system based on FPGA includes a host and an FPGA board connected to the host, and the host includes a CPU, a PCIe driver, and a HOST program;

[0046] The FPGA board is connected to the CPU through the PCIe interface;

[0047] PCIe driver, used to establish the data transmission path between CPU and FPGA;

[0048] The HOST program is responsible for operation analysis and allocation, so that the CPU offloads computationally intensive tasks to the FPGA for execution;

[0049] The FPGA chip is used to offload the computationally intensive tasks from the CPU to perform operations;

[0050] The host also includes a Kernel.lib module and a runtime support library;

[0051] The Kernel.lib module is used to use the runtime support library to realize the distribution of parallel acceleration function files and algorithms.

[0052] The PCIE driver is responsible for establishing the data transmission pat...

Embodiment 2

[0062] Such as image 3 As shown, the embodiment of the present invention provides a kind of FPGA-based domestic platform database acceleration method, comprises the following steps:

[0063] S1: The FPGA loads the configuration file of the statically reconfigured logic module, and cooperates with the PCIe driver to establish a data transmission path between the CPU and the FPGA;

[0064] S2: The host HOST program obtains platform and device information;

[0065] S3: The host HOST program establishes the running context according to the obtained information;

[0066] S4: Copy the data of the established running context to the memory of the board; in this step, the data is copied to the memory of the board through the data path established in step S1.

[0067] S5: The files in the Kernel.lib module are sent to the dynamic reconfigurable logic module in the FPGA, and the data in the memory of the board enters the dynamic reconfigurable logic module. The data is based on the ac...

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Abstract

The invention provides an FPGA-based domestic platform database acceleration system and method, the system comprises a host and an FPGA board card connected with the host, and the host comprises a CPU, a PCIe driver and an HOST program. The FPGA board card is connected with the CPU through a PCIe interface; The PCIe driver is used for establishing a data transmission path between the CPU and the FPGA; The HOST program is responsible for operation analysis and distribution, so that the CPU unloads the compute intensive tasks to the FPGA for execution; The FPGA chip is used for executing the computing intensive tasks unloaded by the CPU; The host also comprises a Kernel. Lib module and an operation support library; and the Kernel. Lib module is used for realizing issuing of a parallel acceleration function file and an algorithm by utilizing the operation support library.

Description

technical field [0001] The invention relates to the technical field of database acceleration, in particular to an FPGA-based domestic platform database acceleration system and method. Background technique [0002] The calculation process of the CPU core requires a large amount of data, and the off-chip DDR not only has limited bandwidth, but also has a long access delay. Although the on-chip cache can alleviate this problem to a certain extent, its capacity is extremely limited. Intel uses a large number of technologies such as data pre-reading, out-of-order execution, and hyper-threading to solve the bandwidth bottleneck and run the CPU as much as possible. However, the complex scheduling design and cache occupy a large amount of CPU silicon chip area, making the logic used for calculations , occupying even less than 1% of the area. At the same time, the constraints of ensuring program compatibility with previous products restrict the evolution of the CPU architecture to ...

Claims

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Application Information

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IPC IPC(8): G06F16/21G06F15/78
Inventor 张武吴登勇李德国
Owner SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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