Semiconductor memory device, operation method thereof, and memory system

Abstract

The application provides a semiconductor memory device, an operation method thereof, and a memory system. The semiconductor memory device includes a memory cell array, an error injection register set,a data input buffer, a write data generator, and control logic. The error injection register set stores an error bit set, including at least one error bit, based on a first command. The error bit setis associated with a data set to be written in the memory cell array. The data input buffer stores the data set to be written in the memory cell array based on a second command. The write data generator generates a write data set to be written in the memory cell array based on the data set and the error bit set. The control logic controls the error injection register set and the data input buffer.

Description

[0001] Cross References to Related Applications [0002] Korean Patent Application No. 10-2017-0145251 entitled "Semiconductor Memory Device, Memory System, and Method of Operating a Semiconductor Memory Device," filed on Nov. 2, 2017, is hereby incorporated by reference in its entirety. technical field [0003] One or more embodiments herein relate to semiconductor memory devices. Background technique [0004] Various semiconductor memories have been developed. Non-volatile memory includes flash memory. Volatile memory includes dynamic random access memory (DRAM). DRAMs are commonly used for system memory because of their high speed operation and cost efficiency. Efforts are continuing to reduce the size of these devices. However, reducing size can increase bit errors and adversely affect yield. Contents of the invention [0005] According to one or more embodiments, a semiconductor memory device includes: a memory cell array; an error injection register set, which s...

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However, reducing size can increase bit errors and adversely affect yield

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