A method of calling data based on fpga off-chip memory
An off-chip memory and data call technology, applied in data conversion, electrical digital data processing, instruments, etc., can solve problems such as low read and write efficiency and inability to meet data call efficiency requirements.
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Embodiment 1
[0024] see figure 1 , which is a flow chart of a method for calling data based on an FPGA off-chip memory provided in this embodiment. A data call method based on FPGA off-chip memory, applied to convolutional neural network, especially the process of extracting data from a feature map with a size of S×S by using a sliding window in the calculation of convolutional neural network, including the following step:
[0025] S1: Set up a fifo group in the FPGA on-chip memory, where the fifo group includes L fifos (first in put first output, first in first output queue), and then number each fifo from 1 to L in sequence, and determine that it needs to be output outside the fifo group at the same time The number M of the fifo of the data, specifically:
[0026] L=2×kernel+Stride×(N-2) (1)
[0027] M=kernel+Stride×(N-1) (2)
[0028] Among them, kernel is the preset convolution kernel size, Stride is the step size of the sliding window used in the convolution calculation, and N is t...
Embodiment 2
[0037] Based on the above embodiment, in this embodiment, the size of the feature map is 15×15, the size of the convolution kernel is 3×3, the step size of the sliding window during the feature map convolution calculation is 1 and the convolution calculation unit on the FPGA chip The number is 2, that is, the number of sliding windows that needs to be processed simultaneously is N=2. As an example, a method for calling an FPGA off-chip memory is described in detail.
[0038] Step 1. Determine the number L of fifos in the fifo group
[0039] Each fifo group is determined according to three parameters: the size of the convolution kernel (kernel), the step size (Stride) of the sliding window during the feature map convolution calculation, and the number of convolution calculation units on the FPGA chip (N). The number L of fifo in , satisfies the following formula:
[0040] L=2×3+1×(2-2)=6
[0041] That is, there are 6 fifos in the fifo group.
[0042] Step 2. Determine the numb...
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