A hardware Trojan horse detection method based on scan chain feature analysis

Abstract

The invention relates to a hardware Trojan horse detection method based on scan chain feature analysis. The method starts with a gate-level netlist of an integrated circuit. The invention provides thehardware Trojan horse detection method based on scan chain feature analysis in a chip design stage. A gate-level netlist of an integrated circuit is firstly converted into a scanning chain netlist, then two new Trojan characteristics are provided by combining the advantages of a traditional circuit characteristic analysis method, and a LightGBM algorithm is utilized to classify a Trojan wire network and a normal wire network. Meanwhile, a machine learning algorithm and a circuit feature analysis method are combined and applied to the hardware Trojan horse detection method, and the method hasthe advantages of being real-time, accurate, low in cost and the like. Aiming at the defects that a traditional hardware Trojan horse circuit feature analysis method is high in time complexity and lowin individual Trojan horse detection efficiency, the scanning chain netlist feature analysis method provided by the invention can improve the detection effect of hardware Trojan horses, and a machinelearning LightGBM algorithm can improve the detection efficiency of the method.

Description

technical field [0001] The invention relates to the field of integrated circuit Trojan horse detection, in particular to a hardware Trojan horse detection method based on scan chain feature analysis. Background technique [0002] With the development of wireless communication, sensor technology, embedded system and microelectronics technology, the safety of integrated circuits has been widely valued by the academic and industrial circles of various countries. [0003] At present, hardware Trojan detection technology can be roughly divided into two categories: formal verification and circuit characteristic analysis, both of which have advantages and disadvantages. [0004] Formal verification is an algorithm-based logic verification method that can exhaustively prove a series of predefined security attribute rules that IC designs should satisfy. For example, the untrusted circuit identification technology proposed by Hicks et al. identifies suspicious circuit nets by looking...

AI Technical Summary

Problems solved by technology

This method has high detection efficiency and low cost, but the detection accuracy and efficiency of the method depend on the selection of Trojan horse features and lack of stability; Channel information is used to find hardware Trojan horses. Unfortunately, it is difficult to obtain "standard" chip samples in reality, and the detection effect of the side channel is heavily dependent on the accuracy of the instrument, which is not suitable for VLSI

Moreover, the side channel method has a weak ability to deal with the interference of process noise, and the denoising processing of bypass noise may affect the original signal again

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