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mems device and method of making the same

A manufacturing method and device technology, which is applied in the manufacture of MEMS devices and in the field of MEMS devices, can solve the problems of failing to meet the performance requirements of MEMS devices, poor uniformity of offspring, and poor uniformity, so as to achieve easy control of the etching process and improve in-plane uniformity sexual effect

Active Publication Date: 2021-01-22
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such thick silicon etching is likely to produce defects with poor uniformity within the wafer (WithinWafer, WIW), so that the height of the formed confinement structure 102 and the bonding substrate layer 102a are also poor in the descendant uniformity, and finally the Less than the performance requirements of MEMS devices

Method used

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  • mems device and method of making the same
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  • mems device and method of making the same

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Embodiment Construction

[0047] like figure 2 Shown is a schematic structural view of the MEMS device of the embodiment of the present invention, and the MEMS device of the embodiment of the present invention includes:

[0048] On the first silicon wafer 1, the main body 3 of the MEMS device is formed on the first silicon wafer 1, the main body 3 of the MEMS device includes a fixed electrode and a movable electrode, and the interval between the fixed electrode and the movable electrode There are grooves.

[0049] On the second silicon wafer 2 , CMOS integrated circuits 9 are formed on the second silicon wafer 2 , and the top of the CMOS integrated circuits 9 are formed with multiple layers of interlayer films, and there are metal layers between the interlayer films of each layer.

[0050] The eutectic bonding is realized between the first silicon wafer 1 and the second silicon wafer 2 through a eutectic bonding structure.

[0051] The first bonding layer of the eutectic bonding structure includes a...

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Abstract

The invention discloses an MEMS device. The MEMS device comprises an MEMS device main part, and a CMOS integrated circuit, wherein the MEMS device main part is formed on a first silicon wafer, and theCMOS integrated circuit is formed on a second silicon wafer; eutectic bonding between the first silicon wafer and the second silicon wafer is realized by a eutectic bonding structure; a first bondinglayer of the eutectic bonding structure comprises a germanium layer formed on the first silicon wafer, and a second bonding layer is the top metal layer formed on the surface of the second silicon wafer; and a limiting structure and a bonding substrate layer formed simultaneously and etched by a first dielectric layer are also formed on the first silicon wafer; the etching in-plane uniformity ofthe first dielectric layer is greater than the silicon etching in-plane uniformity, and the first bonding layer is formed on the surface of the bonding substrate layer and extends to outer silicon andforms contact with the silicon. The invention further discloses a manufacturing method of the MEMS device. The MEMS device and the manufacturing method thereof can improve in-plane uniformity of thedevice, and thus improve performance of the device.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a MEMS device. The invention also relates to a method for manufacturing the MEMS device. Background technique [0002] like Figure 1A to Figure 1F Shown is a schematic diagram of the device structure in each step of the manufacturing method of the existing MEMS device, and the existing method includes the following steps: [0003] like Figure 1A As shown, a silicon wafer 101 is provided. [0004] like Figure 1B As shown, silicon etching is performed to form a stopper 102 on the surface of a silicon wafer 101, and a bonding substrate layer 102a is formed at the same time, and the positions of the two are defined by a photolithography process. Figure 1B In the present invention, the confinement structure 102 is disposed on both side edges of the silicon wafer 101 . [0005] like Figure 1C As shown, sidewalls 102b are formed on the sides of the confinement structure 1...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/18B81B7/02
Inventor 王健鹏
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP