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Three-dimensional stacked system-level packaging process

A system-in-package, three-dimensional stacking technology

Active Publication Date: 2019-07-12
浙江集迈科微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the silicon interposer process requires the use of TSV technology. The processes involved include complex steps such as photolithography, dry etching, PVD, CVD, and electroplating. The cost and technical difficulty are relatively high, and it is not suitable for a large number of civilian products. universal

Method used

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  • Three-dimensional stacked system-level packaging process
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Embodiment Construction

[0034] The embodiments of the present invention are described in detail below, wherein the same or similar reference numerals indicate the same or similar elements or elements with similar functions throughout. The following embodiments described with reference to the accompanying drawings are exemplary, and are only used to explain the present invention but not to limit the present invention.

[0035] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those of ordinary skill in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood as having meanings consistent with the meanings in the context of the prior art, and unless defined as here, idealized or overly formal meanings will not be used To explain.

[0036] The reference numbers of the steps men...

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Abstract

The invention discloses a three-dimensional stacked system-level packaging process comprising the following steps of (101) flexible circuit board manufacturing, (102) functional chip processing, and (103) packaging. The invention provides the three-dimensional stacked system-level packaging process for manufacturing a system-level package structure, the cost is low, the degree of integration is high, and the heat dissipation performance is good.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, and more specifically, it relates to a three-dimensional stacked system-in-package process. Background technique [0002] The rapid development of electronic products is the main driving force for the evolution of packaging technology today. Miniaturization, high density, high frequency and high speed, high performance, high reliability, and low cost are the mainstream development directions of advanced packaging. System-in-a-package is one of the most important and most potential technologies to meet this high-density system integration. [0003] In various system-in-packages, the use of silicon interposer as an intermediate layer is the core technology of silicon-based three-dimensional integrated radio frequency microsystems, which provides the shortest connection distance, smallest pad size and center for chip to chip and chip to substrate spacing. Compared with other interconnectio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/065H01L21/50H01L21/60H01L23/367
CPCH01L21/50H01L23/367H01L24/81H01L25/0657H01L25/50H01L2224/81
Inventor 冯光建刘长春丁祥祥王永河马飞程明芳郭丽丽郁发新
Owner 浙江集迈科微电子有限公司