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EMMC power-down protection test method and system

A test method and test system technology, applied in the direction of static memory, instruments, etc., can solve problems such as failure to protect, data writing errors, abnormalities, etc., to ensure effectiveness, avoid power-down and power-on operations, and facilitate automated testing Effect

Inactive Publication Date: 2019-08-02
FENGHUO COMM SCI & TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] eMMC is a power-down non-volatile memory, which is currently widely used in embedded systems such as mobile phones, tablet computers, and communication devices. In the process of writing data, if eMMC suddenly loses power abnormally, it will cause data loss. Unpredictable problems such as loss, wrong data writing or incomplete data writing cause system abnormalities;
[0003] Usually, eMMC has the function of power-off protection, but this power-off protection cannot protect against all power-off situations. Therefore, in the design of embedded systems, hardware power-off protection circuits and Software related design to enhance the reliability of eMMC;

Method used

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  • EMMC power-down protection test method and system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0046] See figure 1 As shown, Embodiment 1 of the present invention provides a test method for eMMC power failure protection, and the method includes the following steps:

[0047] The method is based on the processor system, eMMC, CPLD, power management chip, and power module. The method includes the following steps:

[0048] S1. The processor system issues a write operation instruction to the eMMC and generates a write operation start signal;

[0049] S2, CPLD detects the write operation start signal, and outputs the power-down operation signal to the power monitoring pin of the power management chip;

[0050] S3. The power management chip controls the power module and performs power-down operations on the eMMC;

[0051] S4. The power management chip controls the power module and powers on the eMMC;

[0052] S5. Detect the eMMC to determine whether the eMMC has abnormal data.

[0053] In the embodiment of the present invention, the processor system and CPLD are used for control, and the ...

Embodiment 2

[0066] Embodiment 2 of the present invention provides a test method for eMMC power failure protection, based on Embodiment 1:

[0067] The write operation start signal is a falling edge signal, that is, the process of the switching signal from 1 to 0, which is used to indicate the start of the write operation;

[0068] It should be noted that in order to accurately power down the eMMC at the instant of the write operation, and thereby accurately verify the effectiveness of the eMMC power-down protection measures, the eMMC write operation signal must be used as the key test determination signal, and the eMMC standard protocol defines , When the eMMC starts a write operation, a falling edge signal will appear on the data line, so the signal that opens the write operation is a falling edge signal.

[0069] In the embodiment of the present invention, the IO pin of the CPLD is configured with a first resistor, which is then connected to the power monitoring pin of the power management chi...

Embodiment 3

[0074] Embodiment 3 of the present invention provides a test method for eMMC power failure protection, based on Embodiment 1:

[0075] CPLD detects the write operation start signal, and outputs the power-down operation signal to the power monitoring pin of the power management chip. CPLD detects the write operation start signal, and after the preset first delay time, it sends the power management chip to the power monitoring tube Pin output power down operation signal;

[0076] The first delay time is set to give the eMMC response time. After confirming that the eMMC receives the write operation start signal, the power-down signal is sent to ensure that the simulation of the power-down state is after the eMMC write operation Carried out, to ensure the validity of the subsequent test results.

[0077] In the embodiment of the present invention, the power management chip controls the power module, and during the power-on operation on the eMMC, the power management chip controls the po...

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Abstract

The invention discloses an eMMC power-down protection test method and system, relates to the technical field of eMMC detection. Based on a processor system, an eMMC, a CPLD, a power management chip and a power module, the method is characterized by comprising the following steps: the processor system issues a write operation instruction to the eMMC to generate a write operation starting signal; the CPLD detects the write operation starting signal and outputs a power-down operation signal to a power monitoring pin of the power management chip; the power management chip controls the power moduleto perform power-down operation on the eMMC; the power supply management chip controls the power supply module to carry out power-on operation on the eMMC; and the eMMC is detected, and whether the eMMC is abnormal in data or not is judged. The eMMC power-down protection test system simulates the working environment of the eMMC, adds the power failure state to the eMMC, carries out artificially controllable power failure state simulation, and then carries out the power-down protection test of the eMMC.

Description

Technical field [0001] The invention relates to the technical field of eMMC detection, in particular to a test method and system for eMMC power failure protection. Background technique [0002] eMMC is a power-down non-volatile memory, which is currently widely used in embedded systems such as mobile phones, tablet computers, and communication devices. When eMMC is writing data, if an abnormal power failure occurs suddenly, it will cause data Unpredictable problems such as loss, data writing error or incomplete data writing cause system abnormalities; [0003] Normally, eMMC has the function of power failure protection, but this kind of power failure protection does not protect against all power failures. Therefore, in the design of embedded systems, hardware power failure protection circuits and Software related design to enhance the reliability of eMMC; [0004] Although there are many ways to prevent the damage caused by abnormal power failure of eMMC, whether it is from the per...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/52G11C29/56
CPCG11C29/52G11C29/56
Inventor 戴权
Owner FENGHUO COMM SCI & TECH CO LTD
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