Method for manufacturing self-aligning graphene transistors by ion implantation oxidation

Abstract

The invention discloses a method for manufacturing self-aligning graphene transistors by ion implantation oxidation. Self-aligning of transistors is realized by combining a composite metal film with the ion implantation technology. The oxidation of a gate medium and the alignment of transistor gate and source / drain are realized by means of region selective ion implantation based on the differencein oxidation performance between different metals and graphene. Parasitic resistance can be reduced, and the exposure of graphene is avoided. A high-quality gate medium can be prepared, and the frequency characteristic of graphene transistors can be enhanced.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to a method for manufacturing self-aligned graphene transistors realized by ion implantation and oxidation. Background technique [0002] Graphene has excellent properties such as high electron mobility and high electron saturation velocity, and has bright application prospects in the high-frequency field. Graphene field-effect transistors are the most basic unit of graphene high-frequency devices, and are also the basis for constructing functional circuits such as low-noise amplifier mixers. [0003] Graphene is used as a conductive layer in the transistor structure. Whether the high electron saturation speed can be brought into play and whether it can be converted into high-frequency performance is the key to its advantages. Starting from the transport characteristics of graphene transistors, the carrier saturation velocity in the channel region is mainly det...

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Problems solved by technology

[0004] The method of optimizing the parasitic resistance of the device is generally to select a metal with a similar work function to reduce the contact and use corrosion self-alignment or gate isolation source-drain self-alignment to reduce the gate-source (drain) series resistance, although this self-alignment method The gate-source (drain) gap can be reduced, but the graphene in the gap area is exposed, and the adsorption of unstable molecules such as water and gas on the graphene surface in the later stage will cause the degradation of transistor performance

In order to reduce interface scattering, the most commonly used preparation method of the gate dielectric is to grow the dielectric by ALD after the metal self-oxidizes to form a buffer. In this process, the self-oxidized buffer layer is generally 1-2nm, and the uniformity and continuity are difficult to control. In the ALD growth process, it has a great influence on the growth rate of the medium

So far, there is no report on a method that can integrate self-alignment and gate dielectric preparation and realize self-alignment

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