3D NAND memory and forming method thereof

Abstract

The invention discloses a 3D NAND memory and a forming method thereof. The forming method comprises the following steps: enabling the density of a pseudo channel through hole in a pseudo channel through hole adjusting region to be greater than that of a pseudo channel through hole in a stepped region outside the pseudo channel through hole adjusting region, wherein the density of a pseudo channel structure in the pseudo channel through hole in the corresponding pseudo channel through hole adjusting region is greater than that of the pseudo channel structure in the pseudo channel through hole in the stepped region outside the pseudo channel through hole adjusting region, and the difference between the density of the pseudo channel structure in the pseudo channel through hole in the pseudo channel through hole adjusting region and the density of the storage structure in the channel through hole in the channel through hole adjusting region is reduced, thereby enabling the difference of the stress of the films in the stacking structure on the two sides or nearby the junction of the step region and the core region to be reduced, enabling the side wall of the gate isolation groove at the junction cannot incline or the inclination to be greatly reduced when the gate isolation groove is formed in the stacking structure at the junction of the etching stepped region and the core region, and preventing the gate isolation groove and the channel through hole from being short-circuited.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for reducing 3D NAND memory. Background technique [0002] NAND flash memory is a non-volatile storage product with low power consumption, light weight and good performance, and has been widely used in electronic products. At present, the NAND flash memory with a planar structure is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory with a 3D structure is proposed. [0003] The formation process of the existing 3D NAND memory generally includes: forming a stacked structure in which isolation layers and sacrificial layers are alternately stacked on the substrate; etching the stacked structure, forming channel vias in the stacked structure, and forming channel vias Finally, etch the substrate at the bottom of the channel via hole to form a groove in the substrate; in ...

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Problems solved by technology

[0004] Existing memories generally include several memory blocks (Blocks), and the memory blocks are generally separated by Gate Line Slits (GLS) vertically penetrating the stacked structure. However, existing 3D NAND memories During the process, the gate spacer in some areas is easy to tilt, resulting in a short circuit between the gate spacer and the channel via hole

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