3d NAND memory and its formation method

Abstract

A 3D NAND memory and a method for forming the same. The forming method is to make the density of the channel vias formed in the channel via adjustment region smaller than that of the channel vias formed in the core region outside the channel via adjustment area. Hole density, so that the difference between the density of dummy channel vias formed in the dummy channel via adjustment area and the density of channel vias formed in the channel via adjustment area is reduced, correspondingly The density of the storage structures in the channel vias in the channel via adjustment area is smaller than the density of the storage structures in the channel vias in the core area outside the channel via adjustment area, so that the junction of the step area and the core area is two The difference in the stress of the film in the side or nearby stacked structure will be reduced, so when the stacked structure at the junction of the etched step region and the core region forms a gate spacer, the junction of the etched step region and the core region will be reduced. The sidewalls of the grid spacer are not inclined or the slope is greatly reduced, thereby preventing the gate spacer from short circuiting with the channel via hole.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND memory and a forming method thereof. Background technique [0002] NAND flash memory is a non-volatile storage product with low power consumption, light weight and good performance, and has been widely used in electronic products. At present, the NAND flash memory with a planar structure is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory with a 3D structure is proposed. [0003] The formation process of the existing 3D NAND memory generally includes: forming a stacked structure in which isolation layers and sacrificial layers are alternately stacked on the substrate; etching the stacked structure, forming channel vias in the stacked structure, and forming channel vias Finally, etch the substrate at the bottom of the channel via hole to form a groove in the subst...

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Problems solved by technology

[0004] Existing memories generally include several memory blocks (Blocks), and the memory blocks are generally separated by Gate Line Slits (GLS) vertically penetrating the stacked structure. However, existing 3D NAND memories During the process, the gate spacer in some areas is easy to tilt, resulting in a short circuit between the gate spacer and the channel via hole

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