3D NAND memory and forming method thereof

Abstract

The invention discloses a 3D NAND memory and a forming method thereof. The forming method is characterized in that the density of channel through holes formed in a channel through hole adjustment region is smaller than the density of channel through holes formed in a core region outside the channel through hole adjustment region, so the difference between the density of pseudo channel through holes formed in the pseudo channel through hole adjusting region and the density of the channel through holes formed in the channel through hole adjusting region is reduced. Correspondingly, the density of storage structures in the channel through holes in the channel through hole adjusting region is smaller than that of the storage structures in the channel through holes in the core region outside the channel through hole adjusting region, so that the stress difference of films in the stacked structures on the two sides or near the junction of the step region and the core region is reduced. Therefore, when the gate isolation groove is formed in the stacked structure at the junction of the etching step region and the core region, the side wall of the gate isolation groove at the junction of the etching step region and the core region is not inclined or the inclination is greatly reduced, so that the short circuit between the gate isolation groove and the channel through hole is prevented.

Description

technical field [0001] The present invention relates to the field of semiconductor fabrication, in particular to a 3D NAND memory and a method for forming the same. Background technique [0002] NAND flash memory is a non-volatile storage product with low power consumption, light weight and good performance, which has been widely used in electronic products. At present, the NAND flash memory with a planar structure is approaching the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory with a 3D structure is proposed. [0003] The formation process of the existing 3D NAND memory generally includes: forming a stack structure in which isolation layers and sacrificial layers are alternately stacked on a substrate; etching the stack structure, forming channel through holes in the stack structure, and forming channel through holes in the stack structure. Then, the substrate at the bottom of the chan...

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Problems solved by technology

[0004] Existing memories generally include several memory blocks (Blocks), and the memory blocks are generally separated by Gate Line Slits (GLS) vertically penetrating the stacked structure. However, existing 3D NAND memories During the process, the gate spacer in some areas is easy to tilt, resulting in a short circuit between the gate spacer and the channel via hole

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