3D NAND memory and formation method thereof

Abstract

The present invention provides a 3D NAND memory and a formation method thereof. In the formation method, the density of a channel through hole formed in a channel through hole regulation region is smaller than that of the channel through hole formed in a core region outside the channel through hole regulation region to reduce the difference between the density of a dummy channel through hole formed in a dummy channel through hole regulation region and the density of the channel through hole formed in the channel through hole regulation region, correspondingly, the density of a storage structure in the channel through hole in the channel through hole regulation region is smaller than that of a storage structure in the channel through hole in the core region outside of the channel through hole regulation region, so that the difference of the stress of a film in stack structures at the two sides of or near the junction of a step region and the core region, when the stack structures at thejunction of the step region and the core region are etched to form a gate isolation groove, the side walls of the gate isolation groove at the junction of the step region and the core region cannot be inclined or the inclination degree is greatly reduced, and it is avoided that the gate isolation groove is in short circuit with the channel through hole.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for reducing 3D NAND memory. Background technique [0002] NAND flash memory is a non-volatile storage product with low power consumption, light weight and good performance, and has been widely used in electronic products. At present, the NAND flash memory with a planar structure is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory with a 3D structure is proposed. [0003] The formation process of the existing 3D NAND memory generally includes: forming a stacked structure in which isolation layers and sacrificial layers are alternately stacked on the substrate; etching the stacked structure, forming channel vias in the stacked structure, and forming channel vias Finally, etch the substrate at the bottom of the channel via hole to form a groove in the substrate; in ...

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Problems solved by technology

[0004] Existing memories generally include several memory blocks (Blocks), and the memory blocks are generally separated by Gate Line Slits (GLS) vertically penetrating the stacked structure. However, existing 3D NAND memories During the process, the gate spacer in some areas is easy to tilt, resulting in a short circuit between the gate spacer and the channel via hole

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