3D NAND memory and method of forming the same

Abstract

A 3D NAND memory and its forming method, the forming method is by making the density of the dummy channel vias in the dummy channel via adjustment area greater than the dummy channel vias in the step area outside the dummy channel via adjustment area Density, the density of the dummy channel structures in the dummy channel vias in the corresponding dummy channel via adjustment area is greater than that in the dummy channel vias in the step area outside the dummy channel via adjustment area , the difference between the density of the dummy channel structures in the dummy channel vias in the dummy channel via adjustment region and the density of the memory structures in the channel vias in the channel via adjustment region is reduced, so that The difference in stress of the thin film in the stacked structure on both sides of or near the junction of the step region and the core region will be reduced, so when the stack structure at the junction of the step region and the core region is etched to form a gate spacer, the junction will be The sidewalls of the gate spacer are not inclined or the inclination is greatly reduced, thereby preventing the gate spacer from being short-circuited with the channel via hole.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for reducing 3D NAND memory. Background technique [0002] NAND flash memory is a non-volatile storage product with low power consumption, light weight and good performance, and has been widely used in electronic products. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory with a 3D structure is proposed. [0003] The formation process of the existing 3D NAND memory generally includes: forming a stacked structure in which isolation layers and sacrificial layers are alternately stacked on the substrate; etching the stacked structure, forming channel vias in the stacked structure, and forming channel vias Finally, etch the substrate at the bottom of the channel via hole to form a groove in the substrate; in the groove at the...

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Problems solved by technology

[0004] Existing memories generally include several memory blocks (Blocks), and the memory blocks are generally separated by Gate Line Slits (GLS) vertically penetrating the stacked structure. However, existing 3D NAND memories During the process, the gate spacer in some areas is easy to tilt, resulting in a short circuit between the gate spacer and the channel via hole

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