Hybrid architecture for signal processing

Abstract

The embodiment of the invention relates to a programmable integrated circuit and a programmable logic system. Systems and methods of configuring a programmable integrated circuit are disclosed. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.

Description

[0001] Instructions for Divisional Application [0002] This application is a divisional application of an invention patent application (named "Hybrid Architecture for Signal Processing") with a filing date of September 22, 2014 and application number 201480063411.3. Background technique [0003] Typically, a programmable logic device (PLD), such as a field programmable gate array (FPGA), includes thousands of programmable logic cells that perform logical operations. For example, each such logic element ("LE") may include a look-up table ("LUT"), registers, and a small number of other circuitry. A LUT can be programmed to generate logic signals, which are any logical combination or function of the LUT's inputs. The LE may be programmable as to whether and how the register is used and what control signals (eg, clock, clock enable, clear, etc.) are selected for application to the register. In addition to LEs, FPGAs typically include interconnect circuitry for communicating si...

AI Technical Summary

Problems solved by technology

However, it is rare that all private blocks are used and sometimes none at all

Some of the main hurdles in adding dedicated blocks to an FPGA are that 1) dedicated blocks are of great benefit to some users, but may sometimes be wasted area for others, and 2) utilize too many different building blocks Families of FPGAs and variants are not cost-effective to manufacture and are often not known until long after the device is defined where dedicated blocks should be included in the design

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