LDMOS device manufacturing method

Abstract

The invention provides a LDMOS device manufacturing method. The LDMOS device manufacturing method comprises the steps of: forming an N type buried layer and a P type epitaxial layer in a P type substrate; forming a field oxygen region on a silicon surface, and then, forming an N well and a P well, wherein the field oxygen region is positioned in the surface region of the N well; forming a grid ona silicon surface between the N well and the P well, wherein the grid and the P well are overlapped longitudinally and partly; and a clearance exists between the grid and the N well longitudinally; forming an N type LDD region at the position of the clearance and positioned on the surface of the P type substrate; forming an N type heavily doped region in the surface region of the P well and the Nwell, and furthermore, forming a P type heavily doped region in the surface region of the P well; and, forming a contact hole in the grid and field oxygen region, and connecting the contact hole to ametal wire. According to the LDMOS device manufacturing method in the invention, a mask does not need to be additionally increased; the existing technical process is utilized; the breakdown voltage BVcan be above 20 V; a certain distance exists between the field oxygen region STI and polycrystalline silicon poly, so that NLDD can be self-aligned and injected; a drift region is composed of NW andNLDD; the contact hole is punched on the STI, so that the effect of a field plate is realized; the technical process is simplified; and the production capacity can be increased.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method of an LDMOS device. Background technique [0002] High-voltage LDMOS is often used in high-voltage power integrated circuits to meet the requirements of high-voltage resistance and power control. LDMOS devices are widely used because they are easily compatible with CMOS processes. Usually, the breakdown voltage BV requires less than 14V for LDMOS, and the drift region can share the N-well NW; but because the implant dose of the N-well NW is relatively thick and difficult to deplete, devices with a BV requirement greater than 14V need to add an additional layer of mask as the LDMOS alone drift zone. [0003] figure 1 It is an LDMOS structure in the prior art, the polysilicon poly field plate straddles the shallow trench isolation region STI, and the drift region is defined by a separate mask mask. Among them, 1-NBL is an n-type buried layer, 2-...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for manufacturing an LDMOS device, which is used to solve the problem of adding an additional layer of mask to the device in the prior art that requires a breakdown voltage greater than 14V as the drift of the LDMOS alone. Areas lead to cumbersome and complicated processes

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