Multi-ADC synchronization device based on phase-locked delay

Abstract

The invention discloses a multi-ADC synchronization device based on phase-locked delay. The method comprises the following steps: firstly, generating clock synchronization signals SYNC and SPI controlcommands through an FPGA; performing initial configuration of a clock generator and a pulse generator under an SPI control command, locking a first-stage phase-locked loop and a second-stage phase-locked loop in sequence, and then realizing synchronous reset signals of multiple ADCs based on a double-cascade type phase-locked loop structure of a clock tree structure connection mode.

Description

technical field [0001] The invention belongs to the technical field of signal processing, and more specifically relates to a multi-ADC synchronization device based on phase-locked delay. Background technique [0002] In high-speed data acquisition systems, multi-ADC parallel acquisition arrays are usually used to increase the sampling rate. In the case of parallel acquisition, the reset of multiple ADCs directly affects the synchronization of ADC output data, and ultimately affects the correct reconstruction of data. Therefore, realizing the stable reset of multiple ADCs and ensuring the acquisition synchronization of multiple ADCs is the key to the design. [0003] Due to the differences in the delay characteristics between the PCB traces of the acquisition board and the discrete components, the delay lengths of the synchronization signals on their respective paths are directly inconsistent. If the synchronization signal is reset in the metastable interval of the sampling...

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Problems solved by technology

Since the PCB routing delay and the delay of discrete components are greatly affected by temperature, when the temperature changes, it is easy to cause the reset signal to act in the metastable state interval or the next reset interval, which will have an adverse effect on the stable reset of the multi-channel ADC.

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