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Preparation method of integrated circuit redistribution layer and semiconductor device

An integrated circuit and redistribution layer technology, which is applied in the field of integrated circuit redistribution layer preparation methods and semiconductor devices, can solve the problems of complex redistribution layer fabrication process and high cost, and achieves the advantages of reducing thickness, strengthening structural strength, and simplifying processing technology. Effect

Inactive Publication Date: 2019-11-12
HOSIN GLOBAL ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a method for preparing an integrated circuit redistribution layer and a semiconductor device for the above-mentioned problems of complex manufacturing process and high cost of the rewiring layer of the integrated circuit

Method used

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  • Preparation method of integrated circuit redistribution layer and semiconductor device
  • Preparation method of integrated circuit redistribution layer and semiconductor device
  • Preparation method of integrated circuit redistribution layer and semiconductor device

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Embodiment Construction

[0021] The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are set forth below to simplify embodiments of the invention. Of course, these are examples only and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, the description below that a first feature is formed "over" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where the first feature is formed in direct contact. Embodiments where an additional feature may be formed between a feature and a second feature such that the first feature may not be in direct contact with the second feature. In addition, the embodiments of the present invention may reuse reference numerals and...

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Abstract

The present invention provides a preparation method of an integrated circuit redistribution layer and a semiconductor device. The method includes: a first sub-layer is formed on an active surface of an integrated circuit body by a 3D printing method; the first sub-layer comprises a first support composed of an insulating material and first signal lines composed of a conductive material; and each first signal line is conductively connected with one or more chip bonding pads on the active surface of the integrated circuit body. The invention rearranges the pads of the integrated circuit throughthe first sub-layer formed by the 3D printing mode; the processing of the redistribution layer is greatly simplified; and the thickness increased by pins is reduced at the same time.

Description

technical field [0001] The invention relates to the field of integrated circuit packaging, and more specifically, relates to a method for preparing an integrated circuit redistribution layer and a semiconductor device. Background technique [0002] Modern products are thin, light and small, so many discrete circuits are integrated into integrated circuits. At present, integrated circuits have been widely used in personal computers, mobile phones, digital cameras, and other electronic devices. In order to provide a stable and reliable working environment for the integrated circuit, and to protect the integrated circuit mechanically or environmentally, so that the integrated circuit can perform normal functions and ensure its high stability and reliability, it is necessary to package the integrated circuit . At present, redistribution layers (Redistribution Layers, RDL) may be used in the packaging structure of various integrated circuits. Through the redistribution layer, t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60H01L23/488
CPCH01L24/02H01L24/03H01L24/06H01L2224/0231H01L2224/02331H01L2224/02373H01L2224/0612H01L2224/11
Inventor 赖振楠
Owner HOSIN GLOBAL ELECTRONICS CO LTD
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