Quick locking phase-locked loop circuit capable of avoiding cycle slip

Abstract

The invention discloses a quick locking phase-locked loop circuit capable of avoiding cycle slip, and belongs to the technical field of integrated circuits. The quick locking phase-locked loop circuitcomprises a phase frequency detector, a charge pump, an intermediate stage circuit, a loop filter, a voltage-controlled oscillator and a frequency divider, wherein the phase frequency detector, the charge pump, the intermediate stage circuit, the loop filter and the voltage-controlled oscillator are connected in sequence; and the output OUT of the voltage-controlled oscillator is connected with the input IN end of the frequency divider, and the output OUT end of the frequency divider is connected with the input IN end of the phase frequency detector to form a feedback path. By adjusting the initial output frequency of the VCO, the quick locking phase-locked loop circuit avoids the situation that when the loop is started, the output clock frequency of the VCO is too close to the expected frequency, namely the reference clock frequency is too close to the feedback clock frequency, so that the locking time is greatly prolonged when cycle slip happens to the loop.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a fast-locked phase-locked loop circuit for avoiding cycle slips. Background technique [0002] Phase locked loop (PLL) is a frequency control system, which is widely used in circuit design, including clock generation, clock recovery, jitter and noise reduction, frequency synthesis and so on. The operation of the PLL is based on the phase difference between the reference clock signal and the feedback of the voltage-controlled oscillator (VCO) output clock signal. The cycle slip refers to that when the frequency of the feedback clock is lower than the frequency of the reference clock, it should be charged at this time, but because the phase of the reference clock lags behind the feedback clock, the charge pump discharges the loop filter instead. Or conversely, when the frequency of the feedback clock is greater than the frequency of the reference clock, it...

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Problems solved by technology

But this also increases the power consumption of the system to a certain extent and increases the complexity of the circuit.

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