High-performance data packet caching method and device based on hierarchical storage

Abstract

The invention discloses a high-performance data packet caching method and a high-performance data packet caching device based on hierarchical storage. The high-performance data packet caching method comprises the following steps that: a data receiving unit of a network processor receives data packet caching data in a network link; an off-chip memory stores cached data of the data packet; when thedata packet is stored, the space needs to be reserved for the head of the data packet instead of starting to store the data packet from the initial address of the space allocated to the off-chip memory by the network processor system; when the network processor modifies the header of the data packet, the header of the data packet is stored in the reserved space, and the whole data packet is storedat the same time; and the data sending unit transmits the stored data packet to a sending network link. According to the invention, in a zero-copy data buffer structure, a large amount of data does not need to be copied and copied, and only the head of the data packet is modified and forwarded before the payload of the data packet, so that the high-speed data processing capability is ensured.

Description

technical field [0001] The invention relates to the technical field of data buffering in network transmission, in particular to a high-performance data packet buffering method and device based on hierarchical storage. Background technique [0002] As the network link rate increases to 40Gbps, network nodes must be able to provide QOS (Quality of Service) control while improving data processing capabilities to meet the needs of various applications. As a network system with storage-processing-forwarding capability, the network processor must first receive the data cache, and then perform protocol processing and forwarding on the data cache. However, in network transmission, the arrival rate of data fluctuates greatly, so a buffer storage unit with large capacity, high bandwidth and fast memory access is required to absorb data fluctuations in the network. [0003] The network processor is produced with the change of network technology application requirements. It has gone th...

AI Technical Summary

Problems solved by technology

[0004] 1. GPP-based network equipment architecture; its advantages: easy to implement function expansion, good flexibility, and low cost; its disadvantages: low performance, not suitable for high-speed network traffic processing;

[0005] 2. Network equipment architecture with ASIC as the core; its advantages: high performance, relying on hardware circuits to realize various network functions; its disadvantages: long design cycle, poor flexibility, and high cost;

[0006] 3. Network device architecture with FPGA as the core; its advantages: it can be changed and erased repeatedly, different functions can be realized in the peripheral circuits without using software, and the type of business processing can be flexibly expanded to a certain extent; its disadvantages: immature technical limitations

[0007] In addition, the multicast of traditional IP data packets requires multiple data copies of the entire data packet during network processing, which will cause a large number of I / O operations on the off-chip memory for caching data packets, which seriously restricts the capacity of the off-chip memory. performance

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