Multi-channel high-speed sampling data synchronous calibration method based on FPGA

Abstract

The invention discloses a multi-channel high-speed sampling data synchronous calibration method based on an FPGA, and belongs to the field of digital signal processing. The multi-channel high-speed sampling data synchronous calibration method based on an FPGA is a method for synchronously calibrating and implementing inter-channel sampling data implemented for multi-channel high-speed sampling, can effectively solve the problem of data synchronization between channels after multi-channel high-speed ADC sampling; the method disclosed by the invention is implemented in the FPGA, and is a processing method for performing sampling cache calibration and realizing a specific synchronization process by FIFO. The method has the advantages of real-time response, high speed and high efficiency, doesnot depend on a hardware platform, does not change sampling clock or ADC kernel parameters depending on existing hardware, does not influence the existing hardware, and performs synchronous calibration at a high-speed sampling rear end before signal processing and analysis.

Description

technical field [0001] The invention belongs to the field of digital signal processing, and in particular relates to a multi-channel high-speed sampling data synchronous calibration method realized based on FPGA. Background technique [0002] With the advancement of chip integrated design technology and processing technology, the application of high-speed sampling above GSPS is becoming more and more common in large-bandwidth signal analysis. Due to the high sampling rate of high-speed sampling systems, front-end analog parts, sampling parts, and back-end signal processing Part of the design and implementation is difficult and demanding, and the amount of real-time data is large, which brings a great burden to the real-time processing and analysis of signals. In practical applications, due to the needs of use, multi-channel high-speed sampling is becoming more and more common. In multi-channel high-speed sampling applications, in addition to the problems caused by the above ...

AI Technical Summary

Problems solved by technology

[0005]Due to limitations in design and processing technology, there is currently no way to adjust the differences between multi-channels in terms of hardware implementation

During the sampling operation, there is currently an operation method to adjust the data synchronization deviation by adjusting the phase relationship of the sampling clocks between channels, but to adjust the phase of the sampling clock, only one sampling clock period can be adjusted, and the adjustment range is narrow. can solve certain situations

In addition, the phase adjustment of the sampling clock will also bring about the asynchronous problem between the sampling clocks. Similarly, in the subsequent channel signal analysis and processing, the problem of asynchronous processing of clock domains between channels due to clock deviation is revealed.

There are also measures to improve the synchronization performance between multiple channels by adjusting the ADC internal channel delay setting, but the adjustable capacity of the ADC internal channel delay setting is also relatively narrow, generally around a maximum sampling clock cycle, which cannot meet the needs of inter-channel The case of large deviation

And some ADCs do not have a channel delay adjustment function inside, which needs to be used depending on the specific device function of the ADC.

There is also a measure of storing the collected multi-channel high-speed sampling data first, and then performing subsequent analysis through the host computer software. This method will not only increase the storage hardware cost, but also cannot meet the requirements of real-time signal processing. Through the host computer software, the synchronous processing and re-analysis of the data between channels will also increase the workload of the software.

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