Convolution operation method and circuit based on CSA adder
A technology of addition operation and convolution operation, which can be used in complex mathematical operations and other directions, and can solve problems such as low efficiency of neural network circuits.
Active Publication Date: 2019-12-20
FUZHOU ROCKCHIP SEMICON
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[0003] For this reason, it is necessary to provide a technical scheme of convolution operation based on CSA adder, in order to solve the problem of low efficiency of the existing neural network circuit when performing convolution operation
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[0051] In order to explain in detail the technical content, structural features, achieved goals and effects of the technical solution, the following will be described in detail in conjunction with specific embodiments and accompanying drawings.
[0052] see figure 1 , is a schematic diagram of a convolutional neural network involved in an embodiment of the present invention. from figure 1 It can be seen from the figure that the neural network includes a convolutional layer, a sampling layer, and a fully connected layer. When calculating a neural network, the convolutional layer and the activation layer are the most computationally intensive. The multiplier involved in the present invention is applied to neural network recognition calculations. Among many calculation types of neural networks, convolution calculations occupy the main part. Convolution calculations include multiplication and addition operations, and multiplication and addition calculations require corresponding ...
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The invention discloses a convolution operation method and circuit based on a CSA adder. The convolution operation circuit comprises a multiplication operation unit, a first additive operation unit, apatch operation unit and a second additive operation unit, wherein he multiplication operation unit comprises a plurality of multipliers. The convolution operation method comprises the steps that a multiplier obtains a first multiplier and a second multiplier for multiplication, and obtains a multiplication result; the first additive operation unit performs first additive operation on the multiplication operation result of each multiplier to obtain an additive intermediate value; the patch operation unit generates patch information corresponding to the multiplication operation result according to the multiplication operation result; and the second additive operation unit is used for executing a second additive operation on each additive intermediate value and each piece of patch information to obtain a convolution operation result. According to the scheme, the patch information is added back at a time when the patch information is calculated firstly and then the additive operation isperformed finally, so that the circuit consumption and the algorithm difficulty are greatly reduced, and the convolution operation efficiency can be effectively improved.
Description
technical field [0001] The invention relates to the field of chip circuits, in particular to a convolution operation method and circuit based on a CSA adder. Background technique [0002] With the rapid development of the artificial intelligence industry, users have higher and higher requirements for the speed of neural network operations. group_convolution (group convolution) is an important algorithm in neural networks, but the corresponding hardware acceleration circuit structure has not been proposed for this algorithm in the prior art. When performing convolution operations, it is still handed over to the CPU to complete, specifically Each group convolution is operated separately according to a convolution task, and the overall operation efficiency is very low. Contents of the invention [0003] For this reason, it is necessary to provide a technical solution of convolution operation based on CSA adder, so as to solve the problem of low efficiency of the existing neu...
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Login to View More IPC IPC(8): G06F17/15
CPCG06F17/15
Inventor 廖裕民张义群
Owner FUZHOU ROCKCHIP SEMICON