A chip packaging method and packaging structure
A chip packaging structure and chip packaging technology, applied in the direction of assembling microstructure devices, microstructure technology, microstructure devices, etc., can solve the problem that the charging method cannot meet people's needs, avoid subsequent shrinkage, ensure circuit performance, and improve The effect of using the area
Active Publication Date: 2020-06-02
HUZHOU JIANWENLU TECH INC
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Problems solved by technology
[0005] In view of this, the present invention provides a chip packaging method and packaging structure to solve the problem that the charging methods limited by charging facilities such as charging piles or charging sockets in the prior art cannot meet people's needs
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[0067] As mentioned in the background art section, as the size of the chip shrinks in the chip package structure in the prior art, the circuit structure also becomes smaller, and the circuit performance cannot be guaranteed.
[0068] The inventors have found that the reason for the above phenomenon is that, as figure 1 As shown, in order to connect the circuit structure to the outside of the chip, it is necessary to set copper pillars 05 between the wafer 01 and the packaging substrate 02, and then form through-silicon vias 04 above the copper pillars, so that the setting of copper pillars 05 occupies a part of the circuit. Due to the space of the structure, the circuit structure needs to be reduced with the reduction of the chip size, and the risk of short circuit between the reduced circuit structures increases, resulting in performance that cannot meet the demand.
[0069] Based on this, the present invention provides a chip packaging method, comprising:
[0070] A wafer i...
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Abstract
The present application provides a chip packaging method and a chip packaging structure. A passivation layer is provided on the pad of the wafer, and then a first bonding layer is formed on the passivation layer, and a second bonding layer is formed on the substrate. The bonding of the first bonding layer and the second bonding layer, the substrate and the wafer are bonded and packaged together. Since a passivation layer is provided between the pad and the bonding layer, the passivation layer makes the pad only serve as a conductive structure , instead of being used as a bonding layer, so that through-silicon vias can be provided above the pads and avoiding the position of the bonding layer to electrically connect the functional circuit area between the wafer and the substrate to the outside of the chip package structure, That is to say, the through-silicon vias are set above the pads, without the need to set copper pillars, and occupy the area of the functional circuit area, thereby increasing the use area of the functional circuit area. When the chip size is reduced, the functional circuit area is prevented from shrinking, thereby ensuring Chip circuit performance.
Description
technical field [0001] The invention relates to the technical field of manufacturing semiconductor devices, in particular to a chip packaging method and packaging structure. Background technique [0002] In the semiconductor chip packaging process, the wafer bonding process is usually used to bond two prepared wafers together through the bonding material, in order to connect the functional circuits on the bonded wafers to the outside , to realize signal transmission, which is realized in various ways in the prior art. [0003] As the volume of semiconductor devices gradually decreases, the TSV (Through Silicon Vias, through silicon via) technology gradually becomes a mainstream technology. Such as figure 1 As shown, it is a schematic diagram of the chip package structure of the surface acoustic wave filter formed by TSV in the prior art; the wafer 01 and the package substrate 02 are bonded together through the bonding glue 03, and then filled with conductive substances 04 ...
Claims
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IPC IPC(8): H01L21/768H01L21/78H01L23/48H03H3/02H03H3/08H03H9/54H03H9/64
CPCH01L21/76898H01L21/78H01L24/94H01L23/481H03H3/02H03H3/08H03H9/64H03H9/54H01L2224/11B81C2203/0118B81B2207/092B81B2207/095B81B2207/097B81C1/00301B81B2207/07H03H9/1014H03H9/1071H01L21/76802H01L21/76877H01L24/03H01L24/11H01L24/16H01L24/27H01L24/29H01L24/83H01L2224/0391
Inventor 李林萍盛荆浩江舟
Owner HUZHOU JIANWENLU TECH INC