Double-T-shaped nano gate and preparation method thereof

Abstract

The invention relates to the technical field of microelectronic devices, and particularly discloses a double-T-shaped nano gate and a preparation method thereof. The double-T-shaped nano gate grows ona substrate with a dielectric passivation layer, and the dielectric passivation layer comprises a bottom dielectric passivation layer and a top dielectric passivation layer; the double-T-shaped nanogate sequentially comprises a gate root, a gate waist and a gate cap from bottom to top. The gate root penetrates through the dielectric passivation layer and grows on the substrate, the gate root isnot in contact with the bottom dielectric passivation layer, and the lower surface of the gate waist is in contact with the upper surface of the top dielectric passivation layer. The grid root and thegrid cap of the double-T-shaped nano grid provided by the invention are suspended; the contact with the dielectric passivation layer is avoided; the top dielectric passivation layer is covered with the gate waist, the stability of the double-T-shaped gate is improved, the distance between the gate cap and the dielectric passivation layer is increased through the double-T-shaped structure, parasitic capacitance can be further reduced, gate inversion caused by the fact that no dielectric support exists during gate stripping is avoided, and the purpose of improving the frequency characteristic of the device is achieved.

Description

technical field [0001] The invention relates to the technical field of microelectronic devices, in particular to a double T-shaped nano-gate and a preparation method thereof. Background technique [0002] The performance of the high electron mobility transistor (HEMT) device is closely related to the processing technology of the device, especially the fabrication of the gate line plays a decisive role in the device. The smaller the gate length, the current cut-off frequency of the device (f T ) The higher the noise figure of the device is, the smaller the noise figure of the device is. People can obtain devices with better characteristics by continuously reducing the gate length of HEMT devices. At present, the gate length of advanced GaAs, InP, and GaN devices at home and abroad has been reduced to less than 100nm. However, as the gate length shortens, the gate resistance increases, and the increase in gate resistance becomes one of the important factors restricting the pe...

AI Technical Summary

Problems solved by technology

[0004] Aiming at the problem of high parasitic capacitance of the dielectric-assisted T-type nano-gate prepared by the existing technology, the present invention provides a double-T-type nano-gate and its preparation method

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