Pole-zero tracking compensation network for voltage regulators

A technology of compensation network and regulator, applied in the field of compensation network

Pending Publication Date: 2020-01-21

INFINEON TECH AUSTRIA AG

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The resulting linear regulator may only be stable (with su...

Method used

[0022] FIG. 1 illustrates an embodiment of an LDO linear voltage regulator 100 comprising an error amplifier 110, a voltage buffer 120, a pass device P1, and a voltage divider comprising resistors R1 and R2 . Power is provided to the voltage regulator 100 from an input 102 having a voltage VIN and at an output 104 to a load. The load of regulator 100 is modeled as a resistor where IL is the load current. Because the current IL drawn by the load varies over time while the voltage VOUT at the output 104 remains substantially constant, the resistance of the load resistor RL varies. A load capacitor CL is also connected to the output 104 and is used to smooth the output voltage VOUT by providing current during load transients, thereby improving the transient performance of...

Abstract

The embodiments of the invention relates to pole-zero tracking compensation network for voltage regulators. Compensation circuits, compensated voltage regulators, and methods are provided for stabilizing voltage regulators, or other circuits that use operational amplifiers, over a wide range of output current. The described techniques provide a zero whose frequency varies linearly with an output current, and which can be used to track and compensate for a pole whose frequency similarly varies with the output current. The variable-frequency zero is created using a compensation capacitor placedin series with a variable resistance, wherein the resistance is configured to vary linearly with the output current. A pole-tracking zero generated in this way may be used to overcome difficulties encountered when the gain of a system includes a pole whose frequency varies with output current, and serves to improve the phase margin of amplifier circuitry, including that used within voltage regulators, and/or serves to ensure stability over a wide range of output current.

Application Domain

Electric variable regulation

Technology Topic

Voltage regulationHemt circuits +7

Image

Examples

Experimental program(1)

Example Embodiment

[0020] The embodiments described herein provide a compensation network and associated methods for compensating the frequency and phase response of a linear regulator to ensure stable operation of the regulator over a wide output current range. The embodiments are mainly described in the context of using a p-channel metal oxide semiconductor field effect transistor (pMOSFET) as a low dropout (LDO) linear regulator of the transfer device. However, the present invention is not limited to LDO regulators based on such transfer devices. For example, the described compensation network can be easily used with LDO regulators using PNP bipolar junction transistors (BJTs) that have similar impedance characteristics (and associated poles) to pMOSFET transfer devices. Furthermore, linear regulators using other types of transfer devices (eg, NPN BJT, n-channel MOSFET) can also advantageously use the compensation network described below. Still further, the described compensation network can be used to stabilize operational amplifiers that are not part of a voltage regulator.

[0021] The embodiments are described below through specific examples of compensation network circuits, linear regulator circuits, and methods for stabilizing amplifiers. It should be understood that the following examples are not meant to be limiting. The circuits and techniques known in the art have not been described in detail so as not to obscure the unique aspects of the present invention. Except where the context does not allow such cases, features and aspects from example embodiments may be combined or rearranged.

[0022] figure 1 An embodiment of the LDO linear voltage regulator 100 is illustrated. The LDO linear voltage regulator 100 includes an error amplifier 110, a voltage buffer 120, a transfer device P1, and a resistor R 1 And R 2 Voltage divider. From having voltage V IN The input 102 provides power to the voltage regulator 100 and the output 104 provides power to the load. The load of the regulator 100 is modeled as a resistor Where I L Is the load current. Because the current drawn by the load I L Change with time, and output voltage V at 104 at the same time OUT Remains basically constant, so the load resistor R L The resistance changes. Load capacitor C L It is also connected to output 104 and used to smooth the output voltage V by supplying current during load transients OUT , Thereby improving the transient performance of the regulator 100. Load capacitor C L Is modeled as having an equivalent series resistance (ESR), which is shown as R ESR. Output voltage V OUT By resistor R 1 And R 2 And reference voltage V REF Set so that

[0023] The illustrated error amplifier 110 is modeled as having a transconductance g ma And output impedance r oa Operational transconductance amplifier (OTA). The buffer 120 is used to isolate the error amplifier 110 from the transfer device P1, and as illustrated, has unity gain and output impedance Use transfer capacitor C P Model the input capacitance of the transfer device P1. Capacitor C can be used BUF Modeling the input capacitance of the buffer 120, the capacitor C BUF It is not explicitly shown for the convenience of description, but it can be regarded as a part of the compensation network 130. Such modeled input capacitance C BUF Will be connected between the input of the buffer 120 and ground.

[0024] The compensation network 130 is connected to the output of the error amplifier 110. Combine image 3 with Figure 5 The embodiment of provides further details regarding the circuitry of the compensation network 130. Before considering these examples, figure 1 The open loop gain of the uncompensated voltage regulator similar to the uncompensated voltage regulator is explained. This open loop gain can be expressed as:

[0025]

[0026] Where g mp Is the transconductance of the transfer device P1, and C BUF Is the parasitic input capacitance of the buffer 120. As shown in equation (1), the uncompensated voltage regulator has three poles and one zero in the following locations:

[0027]

[0028]

[0029] And (4)

[0030]

[0031] As shown in equation (2), the pole p associated with the output node 104 CL (That is, by the load resistor R L And load capacitor C L The pole provided by the parallel connection) has a relationship with the load current I L Directly proportional to the frequency. At the minimum current level "low I L "And the maximum current level "High I L ”Between the load current I L Lead to pole p CL The corresponding frequency shift, such as Figure 2A The Bode plot 200 is illustrated. Bode plot 200 shows that for the load current I L At its minimum level "low I L ”When the amplitude response 210L and phase response 220L. It also shows the load current I L At its maximum level "High I H "When the amplitude response is 210H and the phase response is 220H. It shows the output pole p with low load current and high load current CL Corresponding frequency, as the pole p described in equations (2)-(5) CBUF , Pole p CP And zero point z CL The same frequency. Bode plot 200 also illustrates the effects of other high frequency (HF) poles, but these are not particularly relevant because they occur at frequencies higher than the 0dB gain frequency.

[0032] As shown in Bode plot 200, each pole p CL , P CBUF , P CP Introduce a phase shift of -90°, and the zero point z CL Introduce a phase shift of +90°. The illustrated phase response 220L, 220H relates to a theoretically ideal phase, so that the corresponding phase difference at the 0dB (unit gain) frequency between these responses 220L, 220H and the illustrated negative 180° represents the phase margin of the system . In other words, the illustrated negative 180° represents the worst case without phase margin, and 0° represents the maximum phase margin. As shown in the phase response 220L, for "low I L "There is no phase margin 222L, that is, the phase at the frequency where the gain crosses 0dB is 180° out of phase, which means that the system is unstable for this condition. With "high I L "The phase response 220H corresponding to the current indicates that the phase margin 222H is 45°. For load current levels between these extremes, the phase margin will be between 0° and 45°. This system must be compensated to achieve Accepted stability. However, the pole p CL The frequency change of the sine makes this compensation difficult and/or limits the output current I for stable operation L Range.

[0033] A common technique for stabilizing linear regulators is to select a load capacitor C with high ESR L , So that the corresponding zero point z CL Move lower in frequency. Can be used to select high ESR capacitor C L The alternative or combined with another technology is the introduction of compensation capacitor C C And compensation resistor R C , They are connected to the output of the error amplifier 110. These components provide another zero point, which can be used to compensate the load pole p CL The phase shift. (Compensation capacitor C C And compensation resistor R C Connected in series and internally connected to the regulator instead figure 1 The compensation network 130 shown in. )Compensation capacitor C C Is chosen to be much larger than the input capacitance C of the buffer 120 BUF , Making it possible to ignore the input capacitance C BUF.

[0034] Pass for compensation capacitor C C Choose a sufficiently large capacitor and use the relatively high output impedance of the error amplifier 110 to replace the pole p of the uncompensated system CBUF The compensation pole p Cc Becomes the dominant pole, and has a lower (moving) output pole p CL The frequency of the frequency. (This is in contrast to an uncompensated system, where the pole p CBUF Has an output pole p CL The frequency within the frequency range. ) By the compensation capacitor C C And compensation resistor R C Generated compensation zero point z Cc Can be used to move the output pole p CL The phase shift of is invalid. The resulting loop gain contains three poles and two zeros, as given below:

[0035]

[0036]

[0037]

[0038] And (9)

[0039]

[0040] Figure 2B A typical Bode plot 250 for such a system is shown in. It can be seen in this article that the compensation pole p Cc Is the main pole with very low frequency, and the compensation zero z Cc Falls on the moving output pole p CL , Thus partially compensate the compensation pole p Cc And output pole p CL The phase shift. Respectively with "low I L "And "High I L "The magnitude response 260L, 260H corresponding to the load current is illustrated, just like the phase response 270L, 270H.

[0041] Although the compensated system as described above represents an improvement over the uncompensated system, Figure 2B The Bode plot 250 shows the change in load current I L There are still significant changes in the resulting phase margin. Specifically, the illustrated "low I L "And "High I L "The phase margins of 272L and 272H are 90° and 45° respectively. It is difficult to find the compensation resistor R C A single value of, which can ensure a good phase margin of the entire range between high load current and low load current (P M ). This problem becomes more challenging when the component changes that occur with the process and temperature are also considered. It is worth noting that the load capacitor C L Can have a high tolerance, for example, -20%/+80%, which further widens the output pole p CL Potential frequency range. In order to ensure a stable system (good phase margin), it is necessary to use high-precision and temperature-stable components and/or only support a narrow range of load current I L. Both of these constraints are undesirable.

[0042] Another compensation technique replaces the compensation resistor R described above with a transistor operating in its triode region C , So as to be used as a variable resistor. The conductance of the transistor is controlled based on the load current, thereby providing a zero point that varies with the load current. However, the load pole p CL With output current I L And linear change, this zero point only changes with the output current I L The square root of. Although this provides an improvement over compensation techniques that rely on a fixed zero point, it ensures stable load current I L The range is still not as wide as expected.

[0043] image 3 The variable resistor 340 can be used to generate a zero point, which varies with the load current I L And linear change. Such a zero point can be used to closely track the load pole p CL , The load pole p CL Also varies with load current I L And linear change. By using such a zero point in the voltage regulator 100, a stable load current I L The range of is wider than the stable current range provided by previously known circuits and technologies. In other words, using linear tracking load current I L The zero point provides a better phase margin than other compensation techniques (P M ).

[0044] image 3 The compensation network 330 is illustrated, which includes a variable resistor 340 and a control signal generator 350. The variable resistor 340 can be controlled to provide an output resistance r at node 344 out. The resistance r out At least in the control current I IN Within the selected range and control current I IN Inversely proportional.

[0045] The variable resistor 340 includes a series resistor R S , Parallel resistor R P , And bias current source 342. Bias current source 342 provides constant bias current I B. The transistor N2 is controlled by a series resistor R S Current conduction to determine the current I B How to connect resistor R in series S And parallel resistor R P Distribution between. Transistor N2 is configured to mirror the current I flowing through transistor N1 N1 , So that the current I N1 The final control is in series resistor R S And parallel resistor R P The current divided between, and the resulting output resistance r out. In addition to the transistor N1, the control signal generator 350 also includes an input current source, which provides a typical variable current I IN , And the input bias current sink 352, which absorbs current I IN_BIAS. (The input bias current sink 352 is optional and may not be included in some embodiments. In other embodiments, the current I of the current sink 352 IN_BIAS It can be negative, in which case the current sink 352 provides current. ) For the embodiment including the input bias current sink 352, the current I through the transistor N1 N1 By I N1 = I IN -I IN_BIAS Given.

[0046] To further explain the operation of the variable resistor 340, assume that R S <

[0047] Instead, consider the other extreme, that is, when the input current I IN Very high time. Although the transistor N1 can operate in its saturation (fully conducting) region for this condition, the current I through the transistor N2 N2 By the drain-source voltage V of transistor N2 DS_N2 limits. (This is in Figure 4A Explained further in the description. ) This limit means the current I through transistor N2 N2 Cannot mirror current I correctly N2 , As if both transistors are operating in their saturation region. For this condition, the transistor N2 operates in its triode region, where it can be modeled as having a small resistance R DSON_N2. Assuming that the resistance R DSON_N2 <

[0048] Figure 4A Illustrates a given gate voltage V for transistor N2 GS_N2 , According to the drain-source voltage V of the transistor N2 DS_N2 Drain-source current I N2 The ideal mapping 400. In the triode region, the voltage-current mapping is modeled (approximately) linear. For higher than V DS_N2_SAT Voltage, transistor N2 operates in its saturation mode, where it is approximately the saturation current I N2_SAT Flow through transistor N2 regardless of drain-source voltage V DS_N2 how is it. When the drain-source voltage of transistor N2 V DS_N2 At or above its saturation voltage V DS_N2_SAT , Expressed as The corresponding current level flows through the transistor N1 and is expressed as The associated input current level through the input bias current level I IN_BIAS With current level related.

[0049] For the nominal range Input current I IN , Output resistance r out Is the R of transistor N2 S , R P And output resistance r o_N2 The function. Contrary to the situation described above, the output resistance r of transistor N2 o_N2 It is not negligible for this scenario. The output resistance r in this case out Can be expressed as:

[0050]

[0051] for Input current within the range or equivalently, The transistor N2 will operate in its saturation region and mirror the current I N1. Because transistor N2 operates in its saturation mode, its output resistance r o_N2 Will be very high. More specifically, for the input current range R S <

[0052]

[0053] Resistance r o_N2 It can be approximated by the ratio of the early voltage VE of the transistor N2 to the current flowing through the transistor, that is, corresponding to I N1 = I N2 , (for image 3 In the 1:1 current mirror illustrated in, when both transistors are operating in the same mode, for example, when saturated, the currents through the transistors N1 and N2 should mirror each other. ) Substitute this approximation into equation (12) to obtain:

[0054]

[0055] image 3 The transistors N1 and N2 shown in are n-channel MOSFETs. It should be understood that the circuit topology of the compensation network 330 can be modified to use other types of transistors, for example, pMOSFET, NPN BJT, PNP BJT, to generate current mirrors or the like, and other types of transistors may be preferred in some applications.

[0056] Figure 4B The figure shows that according to I IN The output resistance r out The graph 410. As explained above and shown in Figure 4, the output resistance r out For input current I IN The small value of can be approximated as R P And for I IN The large value of can be approximated as R S ,which is, For the input current I within the nominal range described above IN , Output resistance r out And input current I IN It is inversely proportional, as shown in equation (13) and as shown by the "saturation region" of curve 410. This characteristic of the variable resistor 340 can be used to construct a zero point, which can effectively track and compensate the output pole p CL , Its frequency varies with load current I L And linear movement.

[0057] Figure 5 An LDO voltage regulator 500 is illustrated that uses a variable resistor (such as the variable resistor 340 described above) to introduce a zero point into the gain loop of the regulator 500. The compensation network 530 includes a variable resistor 340, a control signal generator 550, and a compensation capacitor C COMP , The compensation capacitor C COMP The output of the error amplifier 110 is coupled to a variable resistor 340. Compensation capacitor C COMP The capacitance of is much larger than the parasitic input capacitance of the buffer 120, making this parasitic capacitance negligible. The control signal generator 550 uses the current mirrors M1 and M2 to provide a resistance control signal to the transistor N2 of the variable resistor 340. The first current mirror M1 includes a pMOSFET P2, which is configured to mirror the current passing through the pass device P1, which is also a pMOSFET. For specific load resistance R L Much larger values of R1 and R2, typically, the current passing through the device P1 can be approximated as the load current I L. The size of MOSFET P2 and P1 is 1:K, so that the current flowing through MOSFET P2 is approximately The second current mirror M2 includes MOSFETS N2 and N1, the size of which is 1:H. Other transistor types can be used in the first current mirror M1, but the second transistor P2 is typically the same transistor type as the transfer device P1. Other transistor types can also be used in the second current mirror M2.

[0058] Compensation capacitor C COMP With resistance r out The series connection of the variable resistor 340 provides a compensation zero point given by:

[0059]

[0060] As explained earlier and as Figure 4B As shown, the resistance r out In parallel resistance R P High value and series resistance R S Varies between low values. Therefore, the minimum frequency and maximum frequency of the compensation zero point are given by:

[0061] for And (15)

[0062] for Note that according to image 3 Input current shown in I IN versus Figure 5 Load current I L Related, and the currents of transistors N1 and N2 Operate in the same area, where H and K are the current ratios of the current mirrors M1 and M2. In scope Inside, the frequency of the compensation zero can be obtained by combining equations (13) and (14) and considering the current mirror ratio to obtain:

[0063]

[0064] Equation (17) shows that the frequency of the compensation zero point and the load current I L Linearly proportional. Assuming output pole p CL Also with load current I L In linear proportion, the compensation zero provided by the compensation network 530 can track the output pole p very accurately CL.

[0065] Image 6 The Bode plot 600 of the gain loop of the LDO voltage regulator 500 using the compensation network 530 is illustrated. Note that the load current I L From "low I L "Change to "High I L "When the output pole p CL And compensation zero point z COMP The changes in frequency are similar. The phase margin (PM) is kept within a good range and has an impact on the load current I L The dependence is limited. For the illustrated example, "Low I L "Phase margin of 622L and "high I H "The phase margin of 622H is the same, that is, 90°, but the phase margin is equal to that of the output capacitor C L And its resistance R ESR Corresponding zero point z CL Increased to 135°. Note that this is right Figure 2A with Figure 2B The significant improvement in phase margin illustrated in Figure 2A , The phase margin changes from 0° to 45°, and in this Figure 2B , The phase margin changes from 45° to 135°. Through proper selection of component values, the phase margin of the voltage regulator 500 can even be kept constant and is consistent with the load current I L Irrelevant.

[0066] The LDO voltage regulator 500 is very flexible, and the compensation network 530 provides many degrees of freedom, which is not available in the existing compensation technology. Specifically, a series resistor R can be used as needed S , Parallel resistance R P , Input bias current I IN_BIAS And the transistor size ratios H and K to modify the gain loop and associated phase margin. Through proper configuration of these circuit parameters, the frequency response of the LDO voltage regulator can be configured to be at the desired load current I L Meet phase margin or similar requirements within the range. Load current I that can achieve good phase margin L The range is wider than other compensation methods.

[0067] reference Figure 4B , The current I provided by the current sink 352 can be modified IN_BIAS To adjust r out With I IN The transition point 412 between the "cut-off region" and the "saturation region" in the curve. As illustrated by the arrow 414a, the adjustment of the transistor size ratios H and K changes the r in the saturation region out With I IN The slope of the curve. These adjustments similarly modify the switching point 414b between the saturation region and the triode region.

[0068] reference Image 6 , For "high I L "Load current, output pole p CL And compensation zero point z COMP The frequency is aligned. However, for "low I L "Load current, output pole p CL And compensation zero point z COMP The frequencies are not aligned. Bias current I of current sink 352 IN_BIAS , Transistor size ratio H and K, and/or series resistor R S And parallel resistor R P The resistance can be configured to cover the entire load current range (ie, from "low I L "To "High I L ”) within the output pole p CL And compensation zero point z COMP The frequency is aligned.

[0069] Figure 7 The diagram shows the method for frequency compensation of a linear voltage regulator. This method can be implemented in a linear voltage regulator that includes an error amplifier, such as Figure 5 The error amplifier shown in. The linear voltage regulator also includes a compensation network that is coupled to the output of the error amplifier.

[0070] The method 700 begins by sensing 710 the output current of the linear voltage regulator. For example, a current mirror can be used to mirror the current supplied to the load of the voltage regulator. Next, a 720 switch control signal is generated based on the sensed output current. The generated switch control signal is applied 730 to the resistance control switch of the compensation network. This controls the current level flowing through the series resistor of the compensation network, which in turn changes the impedance of the compensation circuit so that the zero point frequency of the compensation network changes linearly with the output current.

[0071] An embodiment of the compensation network includes an input, a first resistance branch, a second resistance branch, and a current source. The input is used to couple to the output of the operational amplifier. The first resistance branch and the second resistance branch are coupled to the output of the operational amplifier. The first resistance branch includes a series resistor, and the second resistance branch coupled in parallel with the first resistance branch includes a parallel resistor. The current source is configured to supply current to the first resistance branch and/or the second resistance branch of the compensation network. The compensation network provides a variable impedance to the input, where the variable impedance includes a resistance that varies between a lower resistance based on the resistance of the series resistor and a higher resistance based on the resistance of the parallel resistor, the variable impedance being based on a resistance control signal. The resistance is based on the resistance control signal.

[0072] According to any embodiment of the compensation network, the first resistance branch includes a resistance control switch connected in series to the series resistor, and the resistance control switch is configured to control the current level through the first resistance branch based on the resistance control signal.

[0073] According to any embodiment of the compensation network, the operational amplifier is an error amplifier within a linear voltage regulator that supplies a load current to the load, and the compensation network further includes a control signal generation circuit configured to generate a resistance control signal based on the load current. According to the first sub-embodiment, the first resistance branch includes a resistance control switch connected in series to the series resistor, and the resistance control switch is configured to control the current level flowing through the first resistance branch based on the resistance control signal. The control signal generation circuit includes a sensing switch configured to mirror the transfer switch of the linear voltage regulator, the load current flows through the transfer switch, and the sense current flows through the sense switch; and the control signal generator switch, which is coupled to the sense switch. The sensing switch allows the sensing current to flow through the control signal generator switch, and the control signal generator switch provides a resistance control signal so that the current level flowing through the resistance control switch mirrors the sensing current. According to a second sub-embodiment, which may or may not be combined with the first sub-embodiment, the variable frequency zero is selected to track the frequency of the pole associated with the output of the linear voltage regulator, where the pole frequency is proportional to the load current.

[0074] An embodiment of a linear voltage regulator includes an input for coupling to an input power source, an output for coupling to a load and load capacitor, a transfer switch, an error amplifier, and a compensation network. The transfer switch is configured to transfer current from the input to the output based on the transfer control signal at the transfer control terminal of the transfer switch. The error amplifier is configured to generate the transfer control signal based on the difference between the reference voltage and the feedback voltage following the output voltage of the linear voltage regulator, and is configured to output the transfer control signal at the error amplifier output. The compensation network is configured as described above and has an input coupled to the error amplifier output of the linear voltage regulator.

[0075] According to any embodiment of the linear voltage regulator, the first resistance branch includes a resistance control switch connected in series to the series resistor, and the resistance control switch is configured to control the current level flowing through the first resistance branch based on the resistance control signal . According to any sub-embodiment, the transfer control signal may be a voltage, and the transfer control terminal may be a gate.

[0076] According to any embodiment of the linear voltage regulator, the current source provides a constant current and is coupled to the first resistance branch and the second resistance branch, so that the constant current flows between the current flowing through the first resistance branch and the current flowing through the second resistance branch. The ratio of these currents is determined by the resistance control signal.

[0077] According to any embodiment of the linear voltage regulator, the linear voltage regulator further includes a compensation capacitor that couples the error amplifier output to the first resistance branch and the second resistance branch.

[0078] According to any embodiment of the linear voltage regulator, the linear voltage regulator further includes a control signal generation circuit configured to generate a resistance control signal based on the load current supplied at the output. According to any sub-embodiments of the linear voltage regulator including the control signal generation circuit, the control signal generation circuit includes a current source. According to any sub-embodiments of the linear voltage regulator including the control signal generating circuit, the first resistance branch includes a resistance control switch connected in series to the series resistor, and the resistance control switch is configured to control the flow through the first resistance control signal based on the resistance control signal. The current level of a resistor branch, and the control signal generating circuit includes a sensing switch configured to mirror the transfer switch, the transfer current flows through the transfer switch, and the sense current flows through the sensing switch; and the control signal generator switch, It is coupled to the sensing switch so that the sensing current flows through the control signal generator switch, and the control signal generator switch provides the resistance control signal, so that the current level flowing through the resistance control switch mirrors the sensing current. According to any sub-embodiments of the linear voltage regulator including the control signal generation circuit, when the control signal generator switch and the resistance control switch are operating in the same mode, the sensing switch and the transfer switch are configured such that the sensing current is more The current is K times smaller, and K is greater than 1, and the control signal generator switch and the resistance control switch are configured such that the current level flowing through the resistance control switch is H times smaller than the sensing current, and H is greater than 1. According to any sub-embodiments of the linear voltage regulator including the control signal generating circuit, the transfer switch and the sense switch are p-channel metal oxide semiconductor field effect transistors (pMOSFET) or the transfer switch and the sense switch are bipolar junction transistors ( BJT).

[0079] An embodiment of the method for frequency compensation of a linear voltage regulator including an error amplifier and a compensation network coupled to the output of the error amplifier includes sensing the output current of the linear voltage regulator, and generating a switch based on the sensed output current control signal. The generated switch control signal is applied to the resistance control switch of the compensation network in order to control the current level flowing through the series resistor of the compensation network. This in turn causes the impedance of the compensation circuit to change, so that the zero frequency of the compensation network changes linearly with the output current. This method produces a zero frequency that varies linearly with the output current of the linear voltage regulator.

[0080] According to any embodiment of the method, the method further includes: supplying a constant current to the compensation network and distributing the supplied constant current between the series resistor and the parallel resistor of the compensation network so that the ratio of these currents is determined by the switch control signal determine.

[0081] According to any embodiment of the method, the impedance of the compensation circuit changes so that the zero frequency of the compensation network tracks the pole frequency of the linear voltage regulator.

[0082] As used herein, the terms "having", "containing", "including", "comprising", etc. are open-ended terms that indicate the presence of the described element or feature, but not Exclude other elements or features. Unless the context clearly dictates otherwise, the articles "a", "an" and "the" are intended to include the plural as well as the singular.

[0083] It should be understood that unless expressly stated otherwise, the features of the various embodiments described herein can be combined with each other.

[0084] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art should appreciate that, without departing from the scope of the present invention, various alternative embodiments and/or equivalent embodiments may be used instead of the illustrated Specific embodiments shown and described. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

PUM

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