3D NAND manufacturing method and memory

Abstract

The invention provides a 3D NAND manufacturing method and a memory. A back etching step of a sacrificial dielectric layer is added before each layer structure deposition step is performed on the channel hole of the 3D NAND structure, the etching area of the sacrificial dielectric layer in the channel hole region is increased, so that the opening area of the sacrificial dielectric layer is increased, and when each layer of structure in the channel, namely an ONOP structure, is formed through subsequent deposition, the ONOP laminated structure is located below the interlayer dielectric layer inthe plane of the sacrificial dielectric layer and plays a role in supporting the interlayer dielectric layer. The nitride layer in the O / N stack structure is subsequently removed and replaced with conductive metal, before a gate line is manufactured and formed, the ONOP structure located between the two adjacent interlayer dielectric layers in the channel hole plays a role in supporting the interlayer dielectric layers, so that the structures of the channel hole and the interlayer dielectric layers are more stable, and the risk that the interlayer dielectric layers are broken or collapsed after the sacrificial dielectric layer in the O / N stack structure is removed is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a 3D NAND manufacturing method and memory. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. [0003] Wherein, in the 3D flash memory of the NOR structure, memory cells are arranged in parallel between the bit line and the ground line, while in the 3D flash memory of the NAND structure, the me...

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Problems solved by technology

[0005] In view of this, the present invention provides a 3D NAND manufacturing method and memory to solve the problem in the prior art that the structural instability in the manufacturing process cannot be guaranteed due to the increase in the number of layers of the O / N stack structure in the 3D NAND flash memory.

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