Security authentication method and system based on security chip and security chip

A security chip and security certification technology, applied in the field of secure communication, can solve problems affecting and affecting information security, and achieve the effect of improving information security and increasing the cost of cracking

Active Publication Date: 2020-03-24
ZHEJIANG GEOFORCECHIP TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, external attackers can choose to observe the communication authentication process, adopt energy analysis attacks, or use special equipment, self-made equipment, exploit security chip design loopholes or software defects, and use various

Method used

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  • Security authentication method and system based on security chip and security chip
  • Security authentication method and system based on security chip and security chip
  • Security authentication method and system based on security chip and security chip

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0051] Example 1

[0052] See figure 1 The security authentication system 1 of the present invention includes a host computer 10 and a security authentication device 11 coupled to the host computer 10; the security authentication device 11 includes a security chip 2 coupled to the host computer 10 and an auxiliary chip 3 coupled to the security chip 2 .

[0053] See figure 2 The security chip 2 includes an MCU core unit 20, a volatile storage unit 21, a non-volatile storage unit 22, an I / O interface 24 and a high-speed hardware algorithm unit; among them, the high-speed hardware algorithm unit includes a high-speed hardware algorithm unit 231, a high-speed hardware algorithm unit Multiple high-speed hardware algorithm units such as the hardware algorithm unit 232 and the high-speed hardware algorithm unit 233. The MCU core unit 20 is mainly used for internal control and operation of the chip, and is usually a general-purpose MCU core such as MSP430 and CORTEX-M0; the volatile sto...

Example Embodiment

[0103] Example 2

[0104] In the description of this embodiment, only the difference between the information processing process of the two chips is exemplarily described, that is, only the difference from the above-mentioned embodiment 1 is explained, and the label of each unit is used in embodiment 1. The label.

[0105] The non-volatile storage unit 32 of the auxiliary chip 3 stores the security key information that has been encrypted, that is, stores the first ciphertext data in Embodiment 1, and is used to decrypt the first ciphertext data. The first decryption key is stored in the nonvolatile storage unit 22 of the security chip 2 in advance.

[0106] That is, in this embodiment, the first ciphertext data is encrypted and generated from the security key data required for security authentication, and the key required for decryption is the aforementioned first decryption key, and the security chip 2 is not required to generate the first random Count and perform symmetric encrypt...

Example Embodiment

[0108] Example 3

[0109] In the description of this embodiment, only the difference between the information processing process of the two chips is exemplarily described, that is, only the difference from the above-mentioned embodiment 1 is explained, and the label of each unit is used in embodiment 1. The label.

[0110] After the auxiliary chip 3 receives the wake-up instruction, it generates a pair of public key and private key based on the asymmetric encryption and decryption algorithm, the private key is stored in the volatile storage unit 31, and the public key is sent to the security chip 2, specifically , The public key can be used as the response information to the wake-up instruction, and the security chip 2 uses the public key to encrypt the first random number using an asymmetric encryption and decryption algorithm to obtain the second ciphertext data and send it to the auxiliary chip 3. The chip uses the private key stored in the volatile storage unit 31 to decrypt, a...

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PUM

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Abstract

The invention relates to a security authentication method and system based on a security chip and the security chip, and belongs to the technical field of security communication. The security authentication method comprises the steps that (1) a security chip sends a key acquisition request to an auxiliary chip in response to a security authentication request sent by an upper computer; (2) the auxiliary chip sends first ciphertext data encrypted by the security key to the security chip in response to the key acquisition request; and (3) the security chip decrypts the first ciphertext data to obtain a security key, and performs security authentication with the upper computer in combination with the code table data stored in the security chip. A security key and code table data required by security authentication are separately stored in a security chip and an auxiliary chip, so that the chip cracking difficulty is increased, the information security is improved, and the method can be widely applied to the field of communication and authentication equipment.

Description

technical field [0001] The invention relates to the technical field of secure communication, in particular to a security chip-based security authentication method and system and the security chip. Background technique [0002] In the field of secure communication technology, in order to provide reliable secure communication protection for Internet of Things (IOT) markets such as home automation, industrial networking, accessories and consumables verification, medical care, and mobile, many manufacturers have adopted encryption countermeasures and security authentication functions. Security chip to effectively provide excellent confidentiality, data integrity and authentication functions for those systems where MCU or MPU runs encryption / decryption algorithms such as ECC in software. [0003] Such as figure 1 Shown is the basic structure of the security chip 2, which mainly includes an MCU core unit 20, a volatile storage unit 21, a non-volatile storage unit 22, a high-speed...

Claims

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Application Information

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IPC IPC(8): G06F21/34
CPCG06F21/34
Inventor 王敏陈志业
Owner ZHEJIANG GEOFORCECHIP TECH CO LTD
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