Method for preparing semiconductor nanostructure through directional self-assembly and mask regulation and control

A directional self-assembly, nano-structure technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., to achieve the effect of reducing heavy dependence and multi-process tolerance

Pending Publication Date: 2020-04-10
CHENGDU TECHCAL UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] The present invention proposes a method capable of preparing high-density semiconductor structures with high reliability, which can greatly overcome the problems caused by

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  • Method for preparing semiconductor nanostructure through directional self-assembly and mask regulation and control
  • Method for preparing semiconductor nanostructure through directional self-assembly and mask regulation and control
  • Method for preparing semiconductor nanostructure through directional self-assembly and mask regulation and control

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[0039] The following definitions and abbreviations are used for the interpretation of the claims and specification. As used herein, the terms "include", "include", "include", "include", "have", "have", "include" or any other variations thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, product or device that includes a series of elements is not necessarily limited to those elements, but may include other elements inherent in the composition, mixture, process, and method that are not explicitly listed or such , Items or equipment.

[0040] As used herein, the articles "a" and "an" before an element or component are intended to be non-limiting with respect to the number of instances (ie occurrences) of the element or component. Therefore, "a" or "an" should be understood to include one or at least one, and the singular form of an element or component also includes the plural, unless the number is obviously singular. The ap...

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Abstract

The invention discloses a method for preparing a semiconductor nanostructure through directional self-assembly and mask regulation and control. The method comprises: forming a double-layer hard mask layer, a photoetching stacking layer and a buffer layer on a semiconductor substrate, spin-coating a block copolymer (BCP) layer on the buffer layer, and annealing to form a self-assembly template pattern; removing a certain block then to form a photoetching pattern, sequentially transferring the pattern to a buffer layer, a photoetching stacking layer and a second hard mask layer, depositing a dielectric layer on the patterned second hard mask layer, flattening, removing the second hard mask layer then, and transferring the pattern to a first mask layer and a semiconductor substrate by takingthe patterned dielectric layer as a mask. According to the method, the problem of directional self-assembly caused by the thickness of the block copolymer and low etching selectivity among different block molecules in the existing pattern transfer process can be greatly solved.

Description

Technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a method for preparing semiconductor nanostructures by directional self-assembly and mask control. Background technique [0002] For more than 50 years, various continuous innovations have promoted the continuous development of the semiconductor industry. Despite many challenges, the history of continuous innovation still maintains Moore's Law. As it becomes increasingly difficult to improve the performance of CMOS devices through continuous scaling, in addition to scaling, other methods for improving device performance have become critical. [0003] Currently, the use of non-planar semiconductor devices, such as semiconductor fin field effect transistors (FinFETs), has been driving the development of CMOS devices since the 22nm technology node. Compared with traditional planar devices, FinFET devices can achieve higher drive currents in smaller and smaller...

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Application Information

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IPC IPC(8): H01L21/8234H01L21/027H01L21/033
CPCH01L21/823431H01L21/0276H01L21/0332H01L21/0338
Inventor 孟令款李可为周波
Owner CHENGDU TECHCAL UNIV
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