Method for preparing semiconductor nanostructure through directional self-assembly and mask regulation and control

Abstract

The invention discloses a method for preparing a semiconductor nanostructure through directional self-assembly and mask regulation and control. The method comprises: forming a double-layer hard mask layer, a photoetching stacking layer and a buffer layer on a semiconductor substrate, spin-coating a block copolymer (BCP) layer on the buffer layer, and annealing to form a self-assembly template pattern; removing a certain block then to form a photoetching pattern, sequentially transferring the pattern to a buffer layer, a photoetching stacking layer and a second hard mask layer, depositing a dielectric layer on the patterned second hard mask layer, flattening, removing the second hard mask layer then, and transferring the pattern to a first mask layer and a semiconductor substrate by takingthe patterned dielectric layer as a mask. According to the method, the problem of directional self-assembly caused by the thickness of the block copolymer and low etching selectivity among different block molecules in the existing pattern transfer process can be greatly solved.

Description

Technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a method for preparing semiconductor nanostructures by directional self-assembly and mask control. Background technique [0002] For more than 50 years, various continuous innovations have promoted the continuous development of the semiconductor industry. Despite many challenges, the history of continuous innovation still maintains Moore's Law. As it becomes increasingly difficult to improve the performance of CMOS devices through continuous scaling, in addition to scaling, other methods for improving device performance have become critical. [0003] Currently, the use of non-planar semiconductor devices, such as semiconductor fin field effect transistors (FinFETs), has been driving the development of CMOS devices since the 22nm technology node. Compared with traditional planar devices, FinFET devices can achieve higher drive currents in smaller and smaller...

AI Technical Summary

Problems solved by technology

[0010] The present invention proposes a method capable of preparing high-density semiconductor structures with high reliability, which can greatly overcome the problems caused by the thickness of block copolymers and low etching selectivity between different block polymer molecules in the existing pattern transfer process. directed self-assembly problem

Images