53 results about "Semiconductor nanostructures" patented technology

An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source / drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source / drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source / drain region from the semiconductor substrate.

The method includes forming a first multilayer stack and a second multilayer stack. The first multilayer stack includes a first plurality of sacrificial layers and a first plurality of semiconductor nanostructures disposed alternately. The second multilayer stack includes a second plurality of sacrificial layers and a second plurality of semiconductor nanostructures disposed alternately. The first plurality of sacrificial layers and the second plurality of sacrificial layers are replaced with a third plurality of sacrificial layers and a fourth plurality of sacrificial layers, respectively. The third plurality of sacrificial layers and the fourth plurality of sacrificial layers are replaced in different processes. The method further includes removing the third plurality of sacrificial layers to form a first recess; forming a first gate stack in the first recess; removing the fourth plurality of sacrificial layers to form a second groove; and forming a second gate stack in the second recess. The embodiment of the invention also relates to a method for forming the semiconductor device.

The invention relates to a continuous high doping concentration in an epitaxial region. A method includes forming a plurality of semiconductor nanostructures. An upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps a corresponding lower semiconductor nanostructure of the plurality of semiconductor nanostructures. The method further includes forming a source / drain recess alongside the plurality of semiconductor nanostructures, where the source / source recess has an intermediate vertical line. A first semiconductor layer is formed from a plurality of semiconductor nanostructures, where the first semiconductor layer includes dopants having a conductivity type, and the conductivity type is p-type or n-type. A second semiconductor layer is formed over the first semiconductor layer, where the second semiconductor has a vertical and elongated high dopant region aligned with an intermediate vertical line. A silicide region coupled with the second semiconductor layer is formed over the second semiconductor layer.

A method includes forming a lower semiconductor nanostructure and an upper semiconductor nanostructure, and forming a lower source / drain region comprising performing a first epitaxy process to grow a first and a second semiconductor isolation layer from the lower semiconductor nanostructure and the upper semiconductor nanostructure, respectively. The method further includes performing a second epitaxy process to grow an epitaxy semiconductor layer from the first semiconductor isolation layer through a bottom-up deposition process, etching the second semiconductor isolation layer to expose a sidewall of the upper semiconductor nanostructure, forming an upper source / drain region starting from the upper semiconductor nanostructure, and, at a time after the upper source / drain region is formed, forming a contact etch stop layer and an inter-layer dielectric in a space between the lower source / drain region and the upper source / drain region.

A method comprises the formation of multiple semiconductor nanostructures. Upper semiconductor nanostructures overlap lower semiconductor nanostructures. The method further comprises the formation of a source / drain cavity adjacent to the semiconductor nanostructures, the source / drain cavity having a central vertical line. A first semiconductor layer is formed from the semiconductor nanostructures, the first semiconductor layer having a dopant of a conductivity type, and the conductivity type being either p-type or n-type. A second semiconductor layer is formed above the first semiconductor layer, the second semiconductor layer having a vertically and elongated heavily doped region aligned with the central vertical line. A silicide region is formed above and electrically coupled to the second semiconductor layer.

This disclosure relates to methods and structures for adjusting gate dielectrics. One method includes forming a plurality of semiconductor nanostructures and forming a hard mask including a top portion over the plurality of semiconductor nanostructures; an inner portion between the plurality of semiconductor nanostructures; and sidewall portions on the sidewalls of the plurality of semiconductor nanostructures. The method further includes etching the sidewall portions of the hard mask, wherein at least the top portion of the hard mask is retained; performing a first oxidation process to oxidize the sidewall portions of the semiconductor nanostructures to form a first oxide layer; removing the top and inner portions of the hard mask; and performing a second oxidation process to oxidize the top and bottom portions of the semiconductor nanostructures to form a second oxide layer. The second oxide layer includes the first oxide layer. The second oxide layer surrounds the remainder of the plurality of semiconductor nanostructures.

A method includes following steps. A first semiconductor nanostructure is formed, and a second semiconductor nanostructure is formed above the first semiconductor nanostructure. First and second gate dielectric layers are respectively formed on the first and second semiconductor nanostructures. A dipole dopant source layer is deposited over the first gate dielectric layer and the second gate dielectric layer. A dummy fill material is formed without performing a CMP process on the dummy fill material. The dipole dopant source layer is etched by using the dummy fill material as an etch mask. After etching the dipole dopant source layer, a dipole dopant of the dipole dopant source layer is incorporated into the first gate dielectric layer.

The embodiment of the invention discloses a semiconductor device and a forming method thereof. The method includes forming a lower source / drain region and an upper source / drain region adjacent to a multilayer stack, the multilayer stack including dummy nanostructures alternately stacked with semiconductor nanostructures, the semiconductor nanostructures including lower semiconductor nanostructures and upper semiconductor nanostructures; removing the pseudo nano structure; forming a first gate dielectric around the lower semiconductor nanostructure, and forming a second gate dielectric around the upper semiconductor nanostructure; forming a first work function metal layer over the first gate dielectric and the second gate dielectric; forming a first metal over the first work function metal layer; performing first etching on the first metal to expose the first work function metal layer; performing a second etch on the first work function metal layer to expose the second gate dielectric; forming a second work function metal layer over the second gate dielectric; and forming a second metal over the second work function metal layer.

A device includes a gate stack having a top portion, and a stacked structure underlying the top portion of the gate stack. The stacked structure includes a plurality of semiconductor nanostructures, with upper nanostructures in the plurality of semiconductor nanostructures overlapping respective lower nanostructures. The stacked structure further includes a plurality of gate structures, each including a lower portion of the gate stack. Each of the plurality of gate structures is between two of the plurality of semiconductor nanostructures. A dielectric layer extends on a top surface and a sidewall of the stacked structure. The dielectric layer includes a lower sub layer comprising a first dielectric material, and an upper sub layer over the lower sub layer and formed of a second dielectric material different from the first dielectric material. A gate spacer is on the dielectric layer. A source / drain region is aside of the gate stack.

In an embodiment, a method includes forming a multilayer stack over a semiconductor substrate, the multilayer stack including alternating semiconductor nanostructures and dummy nanostructures; forming lower source / drain regions, wherein a lower semiconductor nanostructure of the semiconductor nanostructures extends between the lower source / drain regions; forming an upper source / drain region over the lower source / drain region; removing the dummy nanostructures to form a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures; forming a first metal-containing layer around the upper semiconductor nanostructure and in the second opening; exposing a surface of the first metal-containing layer to a first molecular inhibitor to form a first passivation layer on the surface of the first metal-containing layer; and forming a lower gate electrode around the lower semiconductor nanostructure and in the first opening. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

The present disclosure relates to gate dielectrics for nanostructure transistors and methods of forming the same. One method includes forming a plurality of semiconductor nanostructures including a lower semiconductor nanostructure and an uppermost semiconductor nanostructure positioned above the lower semiconductor nanostructure; forming an interface layer in contact with the plurality of semiconductor nanostructures; and depositing a high-k dielectric layer surrounding the interface layer. An uppermost high-k dielectric layer of the high-k dielectric layer surrounding the uppermost semiconductor nanostructure includes an uppermost horizontal portion overlying an uppermost horizontal portion of the uppermost semiconductor nanostructure, a lower horizontal portion underlied by the uppermost semiconductor nanostructure, and a sidewall portion positioned on sidewalls of the uppermost semiconductor nanostructure. A first one of the uppermost horizontal portion, the lower horizontal portion, and the sidewall portion has a first thickness. A second one of the uppermost horizontal portion, the lower horizontal portion, and the sidewall portion has a second thickness less than the first thickness.

A semiconductor device includes a plurality of nanostructured transistor layers in a stacked or vertical configuration. Each nanostructure transistor layer comprises at least one n-type metal oxide semiconductor nanostructure transistor and at least one p-type metal oxide semiconductor nanostructure transistor. Nanostructure transistor layers may be fabricated such that n-type metal oxide semiconductor nanostructure transistors and p-type metal oxide semiconductor nanostructure transistors of two or more nanostructure transistor layers have one or more different characteristics, such as the number of nanostructure channels. This can optimize the performance of n-type metal oxide semiconductor nanostructured transistors and p-type nanostructured transistors of different nanostructured transistor layers for different performance parameters.

The invention discloses a source / drain epitaxial profile and a method for implementing the same. A method includes forming a plurality of semiconductor nanostructures, where an upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps a corresponding lower semiconductor nanostructure of the plurality of semiconductor nanostructures. The method further includes forming a source / drain recess alongside the plurality of semiconductor nanostructures, and forming a first semiconductor layer from the plurality of semiconductor nanostructures. The first semiconductor layer has a convex shape in a cross-sectional view of the first semiconductor layer. A second semiconductor layer is formed over the first semiconductor layer. A silicide region is formed over and in contact with the second semiconductor layer.

The invention relates to the technical field of biomedical sensing and wearable health monitoring, and discloses a photoelectrochemical sensing microneedle, a preparation method thereof, a monitoring system and a detection method. The sensing microneedle comprises a swellable dual-network hydrogel microneedle substrate, a three-dimensional conductive network and a semiconductor nanostructure, wherein the three-dimensional conductive network is composed of high-length-diameter-ratio metal nanowires with a local surface plasma resonance effect, and the semiconductor nanostructure is compounded on the surfaces of the metal nanowires and forms a Schottky heterojunction. The mechanical constraint of the rigid polymer skeleton and the high length-diameter ratio of the metal nanowire cooperate to ensure the continuity of the conductive network in a swelling state. Under the irradiation of exciting light, hot electrons are migrated to the surface of a semiconductor through a Schottky junction built-in electric field to generate reactive oxygen free radicals, non-enzymatic catalytic oxidation is carried out on a target analyte in interstitial fluid under zero bias voltage or low bias voltage, a photocurrent signal is generated, and integration of minimally invasive sampling and in-situ high-selectivity detection is realized.

A method comprises fabricating a plurality of semiconductor nanostructures, wherein the upper layers of the plurality of semiconductor nanostructures overlap the respective lower layers of the plurality of semiconductor nanostructures. The method further comprises creating a source / drain cavity laterally of the plurality of semiconductor nanostructures; and fabricating a first semiconductor layer from the plurality of semiconductor nanostructures. The first semiconductor layer has a convex shape in cross-sectional view. A second semiconductor layer is fabricated above the first semiconductor layer. A silicide region is created above and in contact with the second semiconductor layer.

In an embodiment, a method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack including alternating semiconductor nanostructures and dummy nanostructures; forming lower source / drain regions, where a lower of the semiconductor nanostructures extends between the lower source / drain regions; forming an upper source / drain region over the lower source / drain region, an upper semiconductor nanostructure of the semiconductor nanostructures extending between the upper source / drain regions; forming a gate dielectric layer around the lower semiconductor nanostructure and the upper semiconductor nanostructure; forming a first metal-containing layer over the gate dielectric layer and around the lower semiconductor nanostructure; forming a second metal-containing layer over the first metal-containing layer and around the lower semiconductor nanostructure; and forming a third metal-containing layer over the gate dielectric layer and around the upper semiconductor nanostructure and over the second metal-containing layer. The invention also relates to a semiconductor device and a forming method thereof.

A process involves fabricating a plurality of semiconductor nanostructures, wherein the upper sides of the plurality of semiconductor nanostructures overlap the respective lower sides of the plurality of semiconductor nanostructures. A plurality of semiconductor layers is formed from each of the plurality of semiconductor nanostructures. The plurality of semiconductor layers is shaped by an etching process. A first semiconductor layer of the plurality of semiconductor layers is etched more than a second semiconductor layer of the plurality of semiconductor layers, with the first semiconductor layer being taller than the second semiconductor layer. After the plurality of semiconductor layers has been formed, a further semiconductor layer is fabricated to establish an electrical connection to the plurality of semiconductor layers.

The present disclosure further relates to nanostructures, in particular hybrid nanostructures with patterned growth of various layers for use in nanoscale electronic devices, such as hybrid semiconductor nanostructures with patterned growth and / or deposition of superconducting material for use in quantum devices. The presently disclosed method can be utilized for in-situ manufacturing of nanoscale electronic devices that have not been contaminated by ex-situ processes. One embodiment relates to a method for manufacturing a substrate for growth of crystalline nanostructures, the method comprising the steps of: depositing one or more layers of a crystal growth compatible dielectric material, such as silicon oxide, in a predefined pattern on the surface of a crystal growth compatible substrate to create a predefined etch pattern of said crystal growth compatible material, and selectively etching the substrate surface around said etch pattern to provide at least one under-etched platform which is vertically raised from the etched substrate surface.

A semiconductor device structure is provided. The semiconductor device structure includes an epitaxial structure and a semiconductor nanostructure electrically connected to the epitaxial structure. The semiconductor device structure also includes a metal gate stack extending across the semiconductor nanostructure, and the metal gate stack has a gate dielectric layer and a gate electrode. The semiconductor device structure also includes a protection structure over the metal gate stack and the epitaxial structure. A top of the gate dielectric layer is between a top surface of the protection structure and a bottom surface of the protection structure. A top of the gate dielectric layer is closer to the semiconductor nanostructure than a top of the metal gate stack.

Methods of forming a stacked transistor are provided. One representative method may include patterning a first dummy nanostructure, a second dummy nanostructure, and a semiconductor nanostructure. The semiconductor nanostructure may be disposed between the first dummy nanostructure and the second dummy nanostructure. The first dummy nanostructure may comprise a first semiconductor material and the second dummy nanostructure may comprise a superlattice structure. The representative method may also include performing an etching process that simultaneously recesses the first dummy nanostructure to form a sidewall recess and removes the second dummy nanostructure to form an opening. The etching process selectively etches the superlattice structure at a faster rate than the first semiconductor material. The representative method may further include forming an inner spacer and an isolation structure in, respectively, the sidewall recess and the opening.

Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a plurality of semiconductor nanostructures, a gate stack surrounding each of the semiconductor nanostructures, a gate spacer extending along a sidewall of the gate stack, a first source / drain region electrically connected to a first semiconductor nanostructure of the plurality of semiconductor nanostructures, a semiconductor layer disposed below the first source / drain region, and a first dielectric layer disposed between the first source / drain region and the semiconductor layer. The first dielectric layer includes a first top surface that is concave and a first bottom surface that is substantial flat.

Embodiments of the present invention provide integrated circuits and methods for forming the same. The integrated circuit includes a first nanostructure transistor, the first nanostructure transistor comprising: a plurality of first semiconductor nanostructures located above a substrate; and a source / drain region contacting each of the first semiconductor nanostructures. The integrated circuit also includes a second nanostructure transistor, the second nanostructure transistor comprising: a plurality of second semiconductor nanostructures; and a second source / drain region contacting one or more of the second semiconductor nanostructures, but not contacting one or more other second semiconductor nanostructures.

The embodiment of the invention provides a semiconductor device structure and a forming method thereof. The semiconductor device structure includes: a plurality of semiconductor nanostructures; a gate stack surrounding each of the semiconductor nanostructures; a gate spacer extending along a sidewall of the gate stack; a first source / drain region electrically connected to a first semiconductor nanostructure of the plurality of semiconductor nanostructures; a semiconductor layer disposed under the first source / drain region; and a first dielectric layer disposed between the first source / drain region and the semiconductor layer. The first dielectric layer includes a recessed first top surface and a substantially flat first bottom surface.

In an embodiment, a method includes: forming a multilayer stack including alternating semiconductor nanostructures and dummy nanostructures; forming lower source / drain regions, where a lower of the semiconductor nanostructures extends between the lower source / drain regions; forming an upper source / drain region over the lower source / drain region, with an upper semiconductor nanostructure of the semiconductor nanostructures extending between the upper source / drain regions; removing the dummy nanostructures to form a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures; forming a gate dielectric layer around the lower semiconductor nanostructure and the upper semiconductor nanostructure; forming a lower gate electrode around the lower semiconductor nanostructure and in the first opening; selectively depositing a dummy layer over a top surface of the lower gate electrode, the dummy layer including a first polymer; and forming an upper gate electrode around the upper semiconductor nanostructure and in the second opening. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

A method includes forming a lower source / drain region and an upper source / drain region adjacent to a multi-layer stack, the multi-layer stack comprising dummy nanostructures that are alternatingly stacked with semiconductor nanostructures, the semiconductor nanostructures comprising lower semiconductor nanostructures and upper semiconductor nanostructures; removing the dummy nanostructures; forming first gate dielectrics around the lower semiconductor nanostructures and second gate dielectrics around the upper semiconductor nanostructures; forming a first work function metal layer over the first gate dielectrics and the second gate dielectrics; forming a first metal over the first work function metal layer; performing a first etch on the first metal to expose the first work function metal layer; performing a second etch on the first work function metal layer to expose the second gate dielectrics; forming a second work function metal layer over the second gate dielectrics; and forming a second metal over the second work function metal layer.

A method includes following steps. A first semiconductor nanostructure is formed, and a second semiconductor nanostructure is formed above the first semiconductor nanostructure. First and second gate dielectric layers are respectively formed on the first and second semiconductor nanostructures. A dipole dopant source layer is deposited over the first gate dielectric layer and the second gate dielectric layer. A dummy fill material is formed without performing a CMP process on the dummy fill material. The dipole dopant source layer is etched by using the dummy fill material as an etch mask. After etching the dipole dopant source layer, a dipole dopant of the dipole dopant source layer is incorporated into the first gate dielectric layer.

A method includes forming a plurality of semiconductor nanostructures. Upper ones of the plurality of semiconductor nanostructures overlap respective lower ones of the plurality of semiconductor nanostructures. The method further includes forming a source / drain recess aside of the plurality of semiconductor nanostructures, wherein the source / drain recess has a middle vertical line. A first semiconductor layer is formed from the plurality of semiconductor nanostructures, wherein the first semiconductor layer has a dopant of a conductivity type, and the conductivity type is p-type or n-type. A second semiconductor layer is formed over the first semiconductor layer, wherein the second semiconductor layer has a vertical-and-elongated high-dopant region aligned to the middle vertical line. A silicide region is formed over and electrically coupling to the second semiconductor layer.

A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

A device includes a stack of first semiconductor nanostructures over a substrate and a stack of second semiconductor nanostructures over the substrate. The device includes an isolation structure between the first and second semiconductor nanostructures. The isolation structure includes a core dielectric layer extending from below a top surface of the substrate to a level higher than all of the first and second semiconductor nanostructures. The isolation structure includes a shell dielectric layer surrounding a lower portion of the core dielectric layer and having a top surface lower than all of the semiconductor nanostructures. The spaces between the core dielectric layer and each of the semiconductor nanostructures can be filled with gate dielectric material or with remnants of the shell dielectric layer.