104 results about "Semiconductor nanostructures" patented technology

An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source / drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source / drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source / drain region from the semiconductor substrate.

An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor having a first semiconductor nanostructure corresponding to a channel region of the first semiconductor nanostructure and a first gate metal surrounding the second semiconductor nanostructure. The CFET includes a transistor including a second semiconductor nanostructure above the first semiconductor nanostructure and a second gate metal surrounding the second semiconductor nanostructure. The CFET includes an isolation structure between the first and second semiconductor nanostructures.

A method of forming an integrated circuit includes forming a sacrificial semiconductor nanostructure and a dielectric interposer adjacent to each other between two stacked channels of a gate all around transistor. The method includes forming an inner spacer in contact with the dielectric interposer. The channels are released by removing the sacrificial semiconductor nanostructure and the dielectric interposer.

A method includes forming a transistor, which includes forming a semiconductor nanostructure, forming an interfacial layer encircling the semiconductor region, depositing a dipole film on the interfacial layer, depositing a high-k dielectric layer on the dipole film, and depositing a gate electrode on the high-k dielectric layer. The formation of the transistor may be free from dipole dopant drive-in process and may be free from dipole film removal process.

A method includes forming a multi-layer stack including a plurality of semiconductor nanostructures. The multi-layer stack includes a semiconductor nanostructure, and a sacrificial semiconductor layer over the semiconductor nanostructure. The method further includes depositing a semiconductor layer over and contacting the semiconductor nanostructure, removing the sacrificial semiconductor layer, and forming a replacement gate stack encircling a combined region of the semiconductor nanostructure and the semiconductor layer.

The method includes forming a first multilayer stack and a second multilayer stack. The first multilayer stack includes a first plurality of sacrificial layers and a first plurality of semiconductor nanostructures disposed alternately. The second multilayer stack includes a second plurality of sacrificial layers and a second plurality of semiconductor nanostructures disposed alternately. The first plurality of sacrificial layers and the second plurality of sacrificial layers are replaced with a third plurality of sacrificial layers and a fourth plurality of sacrificial layers, respectively. The third plurality of sacrificial layers and the fourth plurality of sacrificial layers are replaced in different processes. The method further includes removing the third plurality of sacrificial layers to form a first recess; forming a first gate stack in the first recess; removing the fourth plurality of sacrificial layers to form a second groove; and forming a second gate stack in the second recess. The embodiment of the invention also relates to a method for forming the semiconductor device.

The invention relates to a continuous high doping concentration in an epitaxial region. A method includes forming a plurality of semiconductor nanostructures. An upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps a corresponding lower semiconductor nanostructure of the plurality of semiconductor nanostructures. The method further includes forming a source / drain recess alongside the plurality of semiconductor nanostructures, where the source / source recess has an intermediate vertical line. A first semiconductor layer is formed from a plurality of semiconductor nanostructures, where the first semiconductor layer includes dopants having a conductivity type, and the conductivity type is p-type or n-type. A second semiconductor layer is formed over the first semiconductor layer, where the second semiconductor has a vertical and elongated high dopant region aligned with an intermediate vertical line. A silicide region coupled with the second semiconductor layer is formed over the second semiconductor layer.

A method includes forming a lower semiconductor nanostructure and an upper semiconductor nanostructure, and forming a lower source / drain region comprising performing a first epitaxy process to grow a first and a second semiconductor isolation layer from the lower semiconductor nanostructure and the upper semiconductor nanostructure, respectively. The method further includes performing a second epitaxy process to grow an epitaxy semiconductor layer from the first semiconductor isolation layer through a bottom-up deposition process, etching the second semiconductor isolation layer to expose a sidewall of the upper semiconductor nanostructure, forming an upper source / drain region starting from the upper semiconductor nanostructure, and, at a time after the upper source / drain region is formed, forming a contact etch stop layer and an inter-layer dielectric in a space between the lower source / drain region and the upper source / drain region.

A device includes a gate stack having a top portion, and a stacked structure underlying the top portion of the gate stack. The stacked structure includes a plurality of semiconductor nanostructures, with upper nanostructures in the plurality of semiconductor nanostructures overlapping respective lower nanostructures. The stacked structure further includes a plurality of gate structures, each including a lower portion of the gate stack. Each of the plurality of gate structures is between two of the plurality of semiconductor nanostructures. A dielectric layer extends on a top surface and a sidewall of the stacked structure. The dielectric layer includes a lower sub layer comprising a first dielectric material, and an upper sub layer over the lower sub layer and formed of a second dielectric material different from the first dielectric material. A gate spacer is on the dielectric layer. A source / drain region is aside of the gate stack.

A method comprises the formation of multiple semiconductor nanostructures. Upper semiconductor nanostructures overlap lower semiconductor nanostructures. The method further comprises the formation of a source / drain cavity adjacent to the semiconductor nanostructures, the source / drain cavity having a central vertical line. A first semiconductor layer is formed from the semiconductor nanostructures, the first semiconductor layer having a dopant of a conductivity type, and the conductivity type being either p-type or n-type. A second semiconductor layer is formed above the first semiconductor layer, the second semiconductor layer having a vertically and elongated heavily doped region aligned with the central vertical line. A silicide region is formed above and electrically coupled to the second semiconductor layer.

This disclosure relates to methods and structures for adjusting gate dielectrics. One method includes forming a plurality of semiconductor nanostructures and forming a hard mask including a top portion over the plurality of semiconductor nanostructures; an inner portion between the plurality of semiconductor nanostructures; and sidewall portions on the sidewalls of the plurality of semiconductor nanostructures. The method further includes etching the sidewall portions of the hard mask, wherein at least the top portion of the hard mask is retained; performing a first oxidation process to oxidize the sidewall portions of the semiconductor nanostructures to form a first oxide layer; removing the top and inner portions of the hard mask; and performing a second oxidation process to oxidize the top and bottom portions of the semiconductor nanostructures to form a second oxide layer. The second oxide layer includes the first oxide layer. The second oxide layer surrounds the remainder of the plurality of semiconductor nanostructures.

A method includes following steps. A first semiconductor nanostructure is formed, and a second semiconductor nanostructure is formed above the first semiconductor nanostructure. First and second gate dielectric layers are respectively formed on the first and second semiconductor nanostructures. A dipole dopant source layer is deposited over the first gate dielectric layer and the second gate dielectric layer. A dummy fill material is formed without performing a CMP process on the dummy fill material. The dipole dopant source layer is etched by using the dummy fill material as an etch mask. After etching the dipole dopant source layer, a dipole dopant of the dipole dopant source layer is incorporated into the first gate dielectric layer.

The embodiment of the invention discloses a semiconductor device and a forming method thereof. The method includes forming a lower source / drain region and an upper source / drain region adjacent to a multilayer stack, the multilayer stack including dummy nanostructures alternately stacked with semiconductor nanostructures, the semiconductor nanostructures including lower semiconductor nanostructures and upper semiconductor nanostructures; removing the pseudo nano structure; forming a first gate dielectric around the lower semiconductor nanostructure, and forming a second gate dielectric around the upper semiconductor nanostructure; forming a first work function metal layer over the first gate dielectric and the second gate dielectric; forming a first metal over the first work function metal layer; performing first etching on the first metal to expose the first work function metal layer; performing a second etch on the first work function metal layer to expose the second gate dielectric; forming a second work function metal layer over the second gate dielectric; and forming a second metal over the second work function metal layer.

A device includes a gate stack having a top portion, and a stacked structure underlying the top portion of the gate stack. The stacked structure includes a plurality of semiconductor nanostructures, with upper nanostructures in the plurality of semiconductor nanostructures overlapping respective lower nanostructures. The stacked structure further includes a plurality of gate structures, each including a lower portion of the gate stack. Each of the plurality of gate structures is between two of the plurality of semiconductor nanostructures. A dielectric layer extends on a top surface and a sidewall of the stacked structure. The dielectric layer includes a lower sub layer comprising a first dielectric material, and an upper sub layer over the lower sub layer and formed of a second dielectric material different from the first dielectric material. A gate spacer is on the dielectric layer. A source / drain region is aside of the gate stack.

In an embodiment, a method includes forming a multilayer stack over a semiconductor substrate, the multilayer stack including alternating semiconductor nanostructures and dummy nanostructures; forming lower source / drain regions, wherein a lower semiconductor nanostructure of the semiconductor nanostructures extends between the lower source / drain regions; forming an upper source / drain region over the lower source / drain region; removing the dummy nanostructures to form a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures; forming a first metal-containing layer around the upper semiconductor nanostructure and in the second opening; exposing a surface of the first metal-containing layer to a first molecular inhibitor to form a first passivation layer on the surface of the first metal-containing layer; and forming a lower gate electrode around the lower semiconductor nanostructure and in the first opening. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

The present disclosure relates to gate dielectrics for nanostructure transistors and methods of forming the same. One method includes forming a plurality of semiconductor nanostructures including a lower semiconductor nanostructure and an uppermost semiconductor nanostructure positioned above the lower semiconductor nanostructure; forming an interface layer in contact with the plurality of semiconductor nanostructures; and depositing a high-k dielectric layer surrounding the interface layer. An uppermost high-k dielectric layer of the high-k dielectric layer surrounding the uppermost semiconductor nanostructure includes an uppermost horizontal portion overlying an uppermost horizontal portion of the uppermost semiconductor nanostructure, a lower horizontal portion underlied by the uppermost semiconductor nanostructure, and a sidewall portion positioned on sidewalls of the uppermost semiconductor nanostructure. A first one of the uppermost horizontal portion, the lower horizontal portion, and the sidewall portion has a first thickness. A second one of the uppermost horizontal portion, the lower horizontal portion, and the sidewall portion has a second thickness less than the first thickness.

A method includes forming a multilayer stack over a semiconductor region, wherein the multilayer stack comprises a plurality of sacrificial layers and a plurality of semiconductor nanostructures located alternatingly. The method further includes removing the plurality of sacrificial layers, forming a plurality of disposable interposers between the plurality of semiconductor nanostructures, performing an oxidation process on the plurality of disposable interposers, laterally recessing the plurality of disposable interposers to form lateral recesses between the plurality of semiconductor nanostructures, forming inner spacers in the lateral recesses, removing the plurality of disposable interposers, and forming a replacement gate in spaces between the plurality of semiconductor nanostructures.

A semiconductor device includes a plurality of nanostructured transistor layers in a stacked or vertical configuration. Each nanostructure transistor layer comprises at least one n-type metal oxide semiconductor nanostructure transistor and at least one p-type metal oxide semiconductor nanostructure transistor. Nanostructure transistor layers may be fabricated such that n-type metal oxide semiconductor nanostructure transistors and p-type metal oxide semiconductor nanostructure transistors of two or more nanostructure transistor layers have one or more different characteristics, such as the number of nanostructure channels. This can optimize the performance of n-type metal oxide semiconductor nanostructured transistors and p-type nanostructured transistors of different nanostructured transistor layers for different performance parameters.

The invention discloses a source / drain epitaxial profile and a method for implementing the same. A method includes forming a plurality of semiconductor nanostructures, where an upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps a corresponding lower semiconductor nanostructure of the plurality of semiconductor nanostructures. The method further includes forming a source / drain recess alongside the plurality of semiconductor nanostructures, and forming a first semiconductor layer from the plurality of semiconductor nanostructures. The first semiconductor layer has a convex shape in a cross-sectional view of the first semiconductor layer. A second semiconductor layer is formed over the first semiconductor layer. A silicide region is formed over and in contact with the second semiconductor layer.

A method includes forming a shallow trench isolation region aside of a protruding fin. The protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure. The method further includes forming a hard mask on the shallow trench isolation region, forming a dummy gate stack over the protruding fin, removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure, forming a disposable interposer in the space, removing the dummy gate stack, removing the disposable interposer using an etching chemical, wherein when the disposable interposer is removed, the hard mask is exposed to the etching chemical, and forming a gate stack, wherein a portion of the gate stack is filled in the space.

The invention relates to the technical field of biomedical sensing and wearable health monitoring, and discloses a photoelectrochemical sensing microneedle, a preparation method thereof, a monitoring system and a detection method. The sensing microneedle comprises a swellable dual-network hydrogel microneedle substrate, a three-dimensional conductive network and a semiconductor nanostructure, wherein the three-dimensional conductive network is composed of high-length-diameter-ratio metal nanowires with a local surface plasma resonance effect, and the semiconductor nanostructure is compounded on the surfaces of the metal nanowires and forms a Schottky heterojunction. The mechanical constraint of the rigid polymer skeleton and the high length-diameter ratio of the metal nanowire cooperate to ensure the continuity of the conductive network in a swelling state. Under the irradiation of exciting light, hot electrons are migrated to the surface of a semiconductor through a Schottky junction built-in electric field to generate reactive oxygen free radicals, non-enzymatic catalytic oxidation is carried out on a target analyte in interstitial fluid under zero bias voltage or low bias voltage, a photocurrent signal is generated, and integration of minimally invasive sampling and in-situ high-selectivity detection is realized.

A device includes a substrate and a transistor on the substrate. The transistor includes a channel region that has at least one semiconductor nanostructure, and a gate electrode. A source / drain region is disposed adjacent to a first side of the channel region along a first direction. A hybrid fin structure is disposed adjacent to a second side of the channel region along a second direction that is transverse to the first direction. The hybrid fin structure includes a first hybrid fin dielectric layer and a second hybrid fin dielectric layer. The first and second hybrid fin dielectric layers include silicon, oxygen, carbon and nitrogen and have a different concentration of at least one of silicon oxygen, carbon, or nitrogen from one another.

One method comprises creating an STI region (STI: shallow trench insulation) laterally adjacent to a protruding fin. The protruding fin has a first and a second semiconductor nanostructure. The method further comprises: fabricating a dielectric layer on the STI region; fabricating a dummy gate stack over the protruding fin; and performing an implantation process to create a protective layer. The protective layer covers the STI region. A sacrificial layer in the protruding fin is removed, leaving a gap between the first and second semiconductor nanostructures. An exchangeable interposer is fabricated in the gap. The dummy gate stack is then removed, followed by an etching process to remove the exchangeable interposer and the fabrication of a replacement gate stack, with a portion of the replacement gate stack being placed in the gap.

In an embodiment, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure adjacent the first semiconductor nanostructure; a first source / drain region on a first sidewall of the first semiconductor nanostructure; a second source / drain region on a second sidewall of the second semiconductor nanostructure, the second source / drain region completely separated from the first source / drain region; and a source / drain contact between the first source / drain region and the second source / drain region.

A method includes forming a shallow trench isolation region aside of a protruding fin. The protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure. A doping process is performed to dope a dopant into a top portion of the shallow trench isolation region to form a protection layer. The method further includes forming a dummy gate stack over the protruding fin, removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure, forming a disposable interposer in the space. The dummy gate stack is then removed, followed by an etching process to remove the disposable interposer using an etchant. In the etching process, the protection layer is exposed to the etchant. A replacement gate stack is then formed, wherein a portion of the replacement gate stack is filled in the space.

A method includes forming a multilayer stack over a semiconductor region, wherein the multilayer stack comprises a plurality of sacrificial layers and a plurality of semiconductor nanostructures located alternatingly. The method further includes removing the plurality of sacrificial layers, forming a plurality of disposable interposers between the plurality of semiconductor nanostructures, performing an oxidation process on the plurality of disposable interposers, laterally recessing the plurality of disposable interposers to form lateral recesses between the plurality of semiconductor nanostructures, forming inner spacers in the lateral recesses, removing the plurality of disposable interposers, and forming a replacement gate in spaces between the plurality of semiconductor nanostructures.

A semiconductor device structure is provided. The semiconductor device structure includes a channel structure and an epitaxial structure beside the channel structure. The semiconductor device structure also includes a metal gate stack over the semiconductor nanostructures. The metal gate stack includes a gate dielectric layer, a first work function layer over the gate dielectric layer, and a metal oxide layer over the first work function layer. The metal oxide layer is thinner than the first work function layer. The metal gate stack also includes a second work function layer over the metal oxide layer.

A method comprises forming a region of shallow trench isolation adjacent to a protruding fin. The protruding fin has a first semiconductor nanostructure and a second semiconductor nanostructure. The method further comprises: forming a hard mask on the region of shallow trench isolation, forming a dummy gate stack over the protruding fin, removing a sacrificial layer in the protruding fin to leave a space between the first and second semiconductor nanostructures, forming a removable interposer in the space, removing the dummy gate stack, removing the removable interposer using an etching chemical, wherein, when the removable interposer is removed, the hard mask is exposed to the etching chemical, and forming a gate stack, wherein a portion of the gate stack is placed into the space.

A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

The method includes forming a shallow trench isolation region alongside the protruding fin. The protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure. The method further comprises the following steps: forming a dielectric layer on the shallow trench isolation region; forming a dummy gate stack over the protruding fins; and performing an implantation process to form a protective layer. The protection layer covers the shallow trench isolation region. The sacrificial layer in the protruding fins is removed to leave a gap between the first semiconductor nanostructure and the second semiconductor nanostructure. A disposable interposer is formed in the spacing. The dummy gate stack is then removed, followed by an etching process to remove the disposable interposer, and a replacement gate stack is formed, where a portion of the replacement gate stack is filled in the spacer. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.