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Fan-out type semiconductor packaging structure

A packaging structure and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve the problems of improving integration, unfavorable thinning, bump peeling, etc., to improve capacitance and prevent peeling. effect of risk

Inactive Publication Date: 2020-04-10
济南恒耀信息科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The existing assembly methods often use separate capacitors and separate chip packages for secondary packaging, or integrate MIM capacitors in the back-end process of chip manufacturing. For the former, it is not conducive to improving the integration level, while for the latter In terms of, how to effectively use the area of ​​the chip surface to increase the capacitance is the direction of research
Moreover, in the existing method of integrating capacitors in the back-end, the surface of the chip has more dielectric layers and a larger thickness, and the bumps are far away from the chip surface, which is not conducive to thinning, and it is very easy to make the bumps peel off.

Method used

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  • Fan-out type semiconductor packaging structure
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  • Fan-out type semiconductor packaging structure

Examples

Experimental program
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Embodiment Construction

[0025] see Figure 1-3 , the fan-out packaging structure of the present invention integrates a MIM capacitor 8, the MIM capacitor 8 is an annular capacitor, and is formed in the first annular groove 6, and the specific structure includes a chip base 1, which is a board with a chip shape structure, for example, the chip substrate 1 is a silicon substrate with a chip formed inside or an injection molded body with a chip encapsulated in it. The silicon substrate can be obtained by direct singulation of a wafer, and the injection molded body The sealing body of the chip formed by sealing as described in the resin packaging process of the first process, the upper surface of the sealing body must expose the electrical lead-out structure. There are a plurality of pads 2 on the top surface of the chip base 1 , and the pads 2 are lead-out pads of the chip of the chip base 1 .

[0026] The top surface of the chip substrate 1 is provided with a first dielectric layer 3 and a second diel...

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Abstract

The invention provides a fan-out type semiconductor packaging structure. The annular groove structure is formed by using the lower dielectric layer, and the annular MIM capacitor is formed in the annular groove, so that the capacitance is effectively improved, the electric lead-out of the fan-out package is not influenced, the bump is formed in the annular groove, the thinning can be realized on the basis of ensuring the larger volume of the bump, and the stripping risk of the bump is prevented.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a fan-out semiconductor packaging structure. Background technique [0002] Fan-out wafer-level packaging is an embedded chip packaging method for wafer-level processing. It is currently one of the advanced packaging methods with more input / output ports (I / O) and better integration flexibility. Compared with conventional wafer-level packaging, fan-out wafer-level packaging has its unique advantages, so it is widely used. With the functional requirements of packaged devices, chips and capacitors are often required to be interconnected and assembled. The existing assembly methods often use separate capacitors and separate chip packages for secondary packaging, or integrate MIM capacitors in the back-end process of chip manufacturing. For the former, it is not conducive to improving the integration level, while for the latter As far as the chip is concerned, how to effectivel...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L49/02H01L23/522H10N97/00
CPCH01L28/40H01L28/84H01L23/5223
Inventor 侯红伟
Owner 济南恒耀信息科技有限公司