Layout method for three-dimensional FPGA chip

Abstract

The invention relates to a layout method for three-dimensional FPGA chip design. The method comprises the following steps of: simulating a three-dimensional chip by using a planar layout method of thetwo-dimensional chip and a circuit area and the component capacity of the three-dimensional chip, performing hierarchical division of the three-dimensional chip after a two-dimensional planar layoutresult is generated, and vertically superposing all the divided hierarchical layouts into a three-dimensional chip layout. Compared with an existing method, the method has the advantages that the layout quality is better, and the layout result has more solutions; the main workload is concentrated to a two-dimensional simulation part, so that the complexity of software engineering is reduced; the current software process can be better reused, and the development progress of three-dimensional layout software is accelerated.

Description

technical field [0001] The present invention relates to the technical field of field programmable logic gate array (Field Programmable Gate Array, FPGA) chip layout technology, more specifically, the present invention relates to a method for three-dimensional chip layout. Background technique [0002] FPGA is a logic device composed of many logic units, including gates, look-up tables, and flip-flops. It has rich hardware resources, powerful parallel processing capabilities, and flexible reconfigurable capabilities. It is used in data processing, communications, and networks. It has been widely used in many fields. [0003] The design process of the FPGA chip usually includes: design input, debugging, functional simulation, synthesis, layout and routing, timing simulation, configuration download and other steps. Among them, the layout refers to taking the defined logic and input and output blocks from the map and assigning them to the physical locations inside the FPGA. It ...

AI Technical Summary

Problems solved by technology

The 3D chip is a brand new 3D chip. In the current EDA tools and design methods, the method followed by the layout of the 3D chip generally uses the method of first dividing the user netlist, and then performing independent secondary processing on the divided netlists. 3D plane layout, this method cannot optimally match the layout of 3D chips, and has the disadvantages that the layout quality needs to be improved, the current process reuse degree is small, and the software engineering complexity is relatively large.

Images