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OTP memory and manufacturing method thereof

一种制造方法、存储器的技术，应用在只读存储器、静态存储器、半导体/固态器件制造等方向，能够解决不利千位元等级高密度的应用、存储单元面积大等问题，达到读取操作简单且快速、提高写入速度的效果

Active Publication Date: 2022-06-07
HUA HONG SEMICON WUXI LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the existence of the floating gate coupling capacitance in the existing first OTP memory, the storage unit area is too large, which is not conducive to the high-density application of the thousand-bit level

Method used

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  • OTP memory and manufacturing method thereof
  • OTP memory and manufacturing method thereof
  • OTP memory and manufacturing method thereof

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0068] like Figure 4 shown, is the layout of the OTP memory according to the embodiment of the present invention; as Figure 5 shown, is the embodiment of the present invention OTP memory edge Figure 4 The cross-sectional view of the AA line; the cell structure of the OTP memory according to the embodiment of the present invention includes: a first active region 201 and a second active region 202 .

[0069] The first active region 201 and the second active region 202 intersect vertically.

[0070] EDNMOS is formed in the first active region 201 , and PMOS is formed in the second active region 202 .

[0071] The EDNMOS includes a first source region 205, a first channel region 206, a drift region 207, a first drain region 209 and a first gate structure, and the first gate structure consists of a first gate dielectric layer 214a and a first gate dielectric layer 214a. The polysilicon gate 203 is superimposed, the direction between the first source region 205 and the first d...

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PUM

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Abstract

The invention discloses an OTP memory. The unit structure includes: a first active area and a second active area which are vertically intersected; EDNMOS is formed in the first active area, and PMOS is formed in the second active area; The main part of the channel region of PMOS is composed of the drift region of EDNMOS, the first polysilicon gate of EDNMOS is used as the control gate, and the second polysilicon gate of PMOS is the floating gate; the thermal carrier current formed in the drift region of EDNMOS is used The sub-implementation programs the PMOS. The invention also discloses a manufacturing method of the OTP memory. The invention can realize high-speed writing.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a one-time programmable memory (OTP) memory; the invention also relates to a manufacturing method of the OTP memory. Background technique [0002] OTP memory is a common non-volatile memory (NVM), which has many applications in embedded NVM with limited density and limited performance. Traditional Electrically Erasable Programmable Read-Only Memory (EEPROM), SONOS, embedded flash memory (E-Flash) NVM is expensive. OTP memory and CMOS compatible embedded NVM technology is currently a successful solution in the industry and is gaining more and more widespread application at the bit level in applications such as analog fine-tuning all the way to the kilobit level for data or code storage . [0003] There are many types of structural designs of OTP storage units. There are three main types of representative: [0004] The first type is capacitive coupl...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/112
CPCH10B20/30H10B20/25H01L29/7885H01L29/42324H01L21/26513G11C17/08G11C16/0433
Inventor 刘俊文陈华伦
Owner HUA HONG SEMICON WUXI LTD
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