3D memory device and manufacturing method thereof

A manufacturing method and storage device technology, which is applied in the field of memory, can solve problems such as poor device flatness, and achieve the effects of improving flatness, preventing deformation problems, and structural integrity

Active Publication Date: 2020-05-19
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The object of the present invention is to provide an improved 3D memory device and its manufacturing method, by making the top surface of the dummy channel column coplanar with the step surface of the step structure , to solve the problem of poor device flatness

Method used

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  • 3D memory device and manufacturing method thereof
  • 3D memory device and manufacturing method thereof
  • 3D memory device and manufacturing method thereof

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Embodiment Construction

[0034] The present invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, the semiconductor structure obtained after several steps can be described in one figure.

[0035] It should be understood that when describing the structure of the device, when a layer or region is referred to as being "on" or "above" another layer or another region, it can mean directly on the other layer or region, or It also includes other layers or regions between it and another layer or another region. Moreover, if the device is turned over, the layer or area will be "below" or "below" the other layer or area.

[0036] In order to describe the situation of being directly on another layer and another area, this artic...

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Abstract

The invention discloses a 3D memory device and a manufacturing method thereof. The manufacturing method comprises the steps: forming a first laminated structure on a substrate, wherein the first laminated structure comprises a plurality of interlayer insulating layers and gate conductor layers which are stacked alternately, and the first laminated structure is provided with a first step structure;forming a first filling layer covering the first step structure and the substrate; forming a second laminated structure covering the first laminated structure, the second laminated structure comprising a plurality of interlayer insulating layers and gate conductor layers which are alternately stacked, the second laminated structure having a second step structure; and forming a plurality of firstvirtual channel columns, wherein at least a part of the first virtual channel columns are located in the second step structure, and the top surface of at least one first virtual channel column is thestep surface of the second step structure. According to the manufacturing method, the top surface of the virtual channel column and the step surface of the step structure are coplanar, so that the problem of poor flatness of the device is solved.

Description

Technical field [0001] The present invention relates to memory technology, and more specifically, to a 3D memory device and a manufacturing method thereof. Background technique [0002] The development direction of semiconductor technology is the reduction of feature size and the improvement of integration. For storage devices, the increase in storage density of storage devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. [0003] In order to further increase storage density, storage devices with three-dimensional structures (ie, 3D storage devices) have been developed. The 3D storage device includes a plurality of storage cells stacked in a vertical direction, and the integration degree can be doubled on a wafer of unit area, and the cost can be reduced. [0004] In 3D memory devices, gate s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11524H01L27/11529H01L27/11531H01L27/11556H01L27/1157H01L27/11573H01L27/11582
CPCH10B41/42H10B41/41H10B41/35H10B41/27H10B43/40H10B43/35H10B43/27
Inventor 李思晢周玉婷汤召辉张磊曾凡清
Owner YANGTZE MEMORY TECH CO LTD
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